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As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until right before tapeout to run all these checks at once. But how does it actually work and what are the advantages and tradeoffs? This blog post takes a closer look.
Manoj Chacko, product marketing director at Cadence, defines in-design DFM signoff as an approach that "builds DFM engines into the implementation tools, helping designers do DFM signoff checks as they build cells and blocks and move to full-chip implementation. This is so they can detect hot spots early in the implementation flow, and fix them before going to the tapeout signoff step." Thus, in-design DFM signoff extends from standard cell and analog IP design with the Cadence Virtuoso custom design environment to full-chip integration and layout with the Encounter Digital Implementation System.
To understand why this is an important development, let's first consider the traditional IC implementation flow. As shown in the diagram below, at 40nm and below, a new step has been added to the flow - a model-based DFM "signoff" before the design is handed over to a foundry. At that point, it is very likely that lithography hot spots and other violations will be found. These must be fixed before tapeout.
Figure 1 - Traditional DFM signoff flow
If there are only a few hot spots, manual fixes or ECO-style fixes are possible. But if there are over 100 hot spots, which is often the case with complex designs, the only alternative is to re-run the entire flow. That might even be necessary for a single hot spot in a problematic location. Moreover, model-based DFM signoff is extremely time-consuming and computationally intensive.
What if, instead, foundry-certified DFM signoff checks could be run during the IC implementation flow, from cells to complete SoCs? It wouldn't remove the need for that final signoff check, as Chacko noted, but it would make it a lot faster and result in far fewer hot spots that still need to be fixed. The end result is a faster turn-around time due to no or minimal iterations to fix the hotspots, and therefore, a more manufacturable chip.
Does In-Design DFM Slow the Tools?
While the benefits of in-design DFM signoff are evident, I had a question - doesn't the incremental DFM checking slow the implementation tools that are doing it? Yes, Chacko said, but only by a very small amount - and the overall project time savings are still substantial.
He cited an example of a 300micron2 block that was designed in Virtuoso and checked using DRC+, a pattern matching DFM signoff flow for 28nm developed and qualified by GLOBALFOUNDRIES (and described in my previous blog post). It took around 5 seconds to find 23 hot spots and fix all of them. Running model-based simulation on that block took around 8-10 minutes, far longer to be sure, but still, as Chacko noted, "the marginal cost of running DFM signoff in design is a lot less than the cost of running it at signoff."
In an Encounter example, incremental DFM checking at 28nm resulted in a 4% longer run-time during routing, including pattern matching and automatic fixing of all hot spots. The diagram below shows how routing works with in-design DFM. Basically, NanoRoute takes in a placed database, uses built-in lithography error prevention, and then allows the user to choose a pattern matching based flow or a "near signoff" Turbo Litho analysis that is both pattern-based and model-based, depending on the end foundry. Any remaining hot spots are then analyzed and fixed with Cadence Litho Physical Analyzer (LPA), using a foundry-qualified full signoff engine.
Figure 2 - Encounter In-design DFM convergent routing flow
In addition to LPA, foundry qualified in-design DFM also works with Layout Electrical Analyzer (LEA) and Cadence CMP Predictor (CCP), in both the Virtuoso and Encounter environments. In Virtuoso, for example, the CMP analysis is block-based, taking into account many possible layout configurations to estimate appropriate metal fill configurations. CCP also offers signoff CMP analysis after placement and routing, and before timing signoff, in the Encounter flow.
Solution for Advanced Nodes
One of the big problems with advanced nodes (28nm and below) is the prevalence of layout-dependent effects (LDE), in which transistor characteristics change according to the location of nearby devices. Current solutions for analyzing the impact of layout-dependent effects on the transistor performance are based on the traditional signoff flow which involves layout-versus-schematic (LVS) checking, parasitic extractions and then SPICE.
In-design LDE analysis with Virtuoso DFM offers the ability to perform a simple check prior to the traditional signoff flow and gives layout designers the ability to identify transistors impacted due to LDE effects and correct them. This helps to reduce the number of loops in the signoff flow (LVS-extraction-simulation), thereby bringing significant design cycle time reduction.
For library designers, LEA can run cells in hundreds of random layout contexts, and create a "score" that is passed along to Encounter for cell placement. Encounter then provides context-aware placement, which uses this score to reduce sensitivity to lithography and stress variation on critical paths. Further, Encounter runs a layout dependent effect-aware, path-based timing analysis, making it possible to optimize critical paths to reduce sensitivity to layout-dependent effects.
Is there a greater need for in-design DFM signoff at 28nm and below? "Absolutely," Chacko said. He noted that the average GDSII file size, number of layers, and number of masks are increasing dramatically at every new process node, with files of 20 GBytes per layer commonplace. This translates into much longer run times for signoff steps. What will be needed in the future, he noted, is interactive signoff in addition to batch-based signoff.
A Bigger Picture
In-design DFM signoff is part of a larger "in design signoff" picture at Cadence, which also includes parasitic extraction, physical verification, static timing analysis, and power integrity analysis. See Pete McCrorie's blog post for a good summary.