Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
You may have heard that "virtual platforms" enable software development and debugging before system hardware is available. But how do you build them, how do you solve common problems, and how do you debug software and hardware for multi-core systems? These questions and more were answered in a paper presented at the recent ARM TechCon conference by Jason Andrews, senior architect at Cadence.
The paper was titled "Creation and Usage of SystemC Virtual Platforms for Multi-Core System Debugging and Analysis," and was given Oct. 27. Proceedings are available to conference attendees at the ARM TechCon web site. A video of the presentation is available here and is also embedded below.
A virtual platform, Andrews noted, makes it possible to simulate hardware using SystemC, and to then run software on top of that simulated hardware. "It's all simulation," he noted. "Everything you'll hear about today runs on a workstation - no boards, no cables." While simulation has been used for software development for many years, the commercial virtual platform market is relatively new. Two standards that make this possible are SystemC (IEEE 1666), a set of classes on top of C++, and the Open SystemC Initiative (OSCI) transaction-level modeling (TLM 2.0) standard, which permits a high level of modeling abstraction.
As shown in the following diagram of the Cadence System Development Suite, virtual platforms are part of a larger hardware/software development continuum, and are used very early in the design flow:
To show how virtual platforms are created and how they work, Andrews used an example of a multi-core design. It includes a dual ARM Cortex-A9 processor with an L2 cache, an ARM Cortex-M3 processor, LPDDR2 controller, SRAM, ROM, UART, and timers, among other components. He then walked through a detailed example showing how a virtual platform was created for this design. Some of the key steps included:
What you end up with is a virtual platform that contains Fast Models for the ARM processors and SystemC models for all the peripherals. The ARM models take binary instructions and run software on a laptop or workstation at a very high rate of speed.
When designers plug everything together, Andrews said, "it never works" the first time. He reviewed a number of common problems that arise with virtual platforms. These include system integration issues such as a program memory that's too small, device driver crashes due to missing hardware, and problems with interrupts. The Direct Memory Interface (DMI), which lets SystemC models read directly into memory, is also a potential source of problems. Andrews also reviewed common problems made during model creation.
Andrews then showed how to set up a secure boot sequence for the Cortex-A9 and Cortex-M3, and reviewed potential problems such as poor synchronization of access to shared RAM and difficulties with the interrupt configuration.
Virtual Platform Debugging
Once the platform Is set up and simulation is running, designers will want to start debugging. "The first thing everybody tries is debugging software," Andrews noted. This can be done with a software debugger that shows what's going on in the various processor cores, displays register values, allows single-stepping, and provides other features one would expect from a software debugger. But just looking at software may not enough. Multi-core systems use frequent interrupts, and problems with interrupts are common.
"Now you're thinking you want something like a logic analyzer, and you want to see all the interrupt lines," Andrews said. "Well, in a virtual platform you can see hardware behavior that is harder to see on your board." This was a common theme in the presentation - that virtual platforms make it possible to observe hardware behavior that would be difficult to see in real hardware.
Andrews talked about the profiling capabilities available with virtual platforms, which can be used both to improve simulation speed and to make the system software and hardware implementation more efficient. While it's not easy to profile using real hardware, he noted, a virtual platform allows non-intrusive profiling without the need to instrument code. (For more information on profiling see Andrews' guest blog on the ARM web site, "Using the ARM Profiler with the Cadence Virtual System Platform.")
"For me, creating this type of virtual platform is fun," Andrews concluded. "You learn a lot and you see how things work." He also noted that a lot of companies are training or looking for "virtual platform engineers" who can create and debug the models. It's a chance to "be the hub for all the engineers working on your project," he said.
Click on the icon below to view the video of the presentation, or click here.
Other blog posts about ARM TechCon 2011 papers:
ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs
ARM TechCon Paper: "Tips and Tricks" for ARM Cortex-A15 Designs
ARM TechCon Paper: Why DRAM Latency is Getting Worse