Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
You might think that an IC digital implementation toolset, such as the Cadence Encounter Digital Implementation System, is only useful after RTL is developed and synthesized. But that's not necessarily the case. At the recent ARM TechCon conference, Cadence and Cisco Systems presented a flow that Cisco is using to do pre-RTL architectural analysis with Encounter.
The paper was titled "Early Architectural Planning for Increased Productivity, Predictability and Profitability," and was presented by Abha Maheshwari, product manager at Cadence, and Krishna Kumar, senior hardware engineer at Cisco. Proceedings are available to conference attendees at the ARM TechCon web site.
In brief, the flow captures design and technology information in a text file, uses a Tcl script to create a netlist, and then uses the automated floorplan synthesis capability in Encounter to generate an early floorplan. Cisco engineers can then obtain early die size and cost estimates, try different architectural alternatives, and develop a preliminary floorplan that can be provided to an ASIC vendor.
"Using our place and route solution and some scripts, we've been able to come up with a complete flow to do architectural analysis very early in the design stage before you even have any RTL ready," Maheshwari said. She summarized the advantages of this approach in the following slide:
Kumar then talked about Cisco's motivations for adopting early architectural analysis. He noted that his group targets different market segments with its networking ASICs, and must meet different requirements. Further, at advanced nodes, wire delays are dominating cell delays. "This means your top level implementation is going to be much more critical," he said. "The best way is to start very early in the design cycle, without coding any RTL, and do an analysis of the design and find out where the bottlenecks are."
Kumar walked through the architectural analysis flow in detail. It starts with the capture of chip architecture and IP information in a text file. Then, a simple Tcl script creates a netlist from this early architectural information. The script adds dummy cells, dummy flops, dummy or real memory, pipeline stage registers, timing constraints, and clock definitions.
An interactive schematic visualization capability in Encounter lets designers view and check the connectivity between different modules. The Encounter GUI can also help designers analyze the implementation feasibility of dummy memory and IP elements. Additionally, Encounter helps Cisco engineers verify pipeline flip-flop insertion, and set up bus guides and net groups.
The next step is automated floorplan synthesis, which was described by Maheshwari. She showed how this capability can take in seed information (or generate its own), optimize the data path, place modules and hard macros, and "provide a very good starting point floorplan in a short amount of time." Designers can generate multiple floorplans and select the best one to meet their goals.
From Two Months to Two Weeks
During his presentation, Kumar noted that prior to using the early architectural flow, Cisco would sometimes wait 2-3 months for an ASIC vendor to come back with die size and cost information. "Right now we are able to do this in two weeks, because everything is done in house without any RTL," he said. Today, he noted, Cisco and Cadence are working together to develop and strengthen capabilities such as automatic bus guide creation, identification and placement of pipeline flops, and what-if analysis for the top-level pipeline. Present and future Encounter Digital Implementation System users will benefit from this work.
Other blog posts about ARM TechCon 2011 papers:
ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs
ARM TechCon Paper: "Tips and Tricks" for ARM Cortex-A15 Designs
ARM TechCon Paper: Why DRAM Latency is Getting Worse
ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development