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For some time Cadence has offered EDA360 "Technology on Tour" presentations in various cities. Now Cadence is offering on-line Technology on Tour presentations at your desktop, any time, for free. These technical presentations and demos show how to solve common design challenges, and provide the latest information about Cadence custom/analog, digital, and PCB design technologies.
Most of the presentations are in the 30 minute to one hour range, although a few are shorter. Many include both slide presentations and demos. The sessions are available to Cadence Community members (quick, free registration if you're not one yet). You can also sign up for live chat sessions at scheduled times.
To get a feel for these offerings I watched a presentation on trends in 28nm design by Wei Lii Tan, senior product marketing manager at Cadence. In this informative, 40-minute presentation, Tan identified three 28nm challenges - design size and complexity, timing variability, and manufacturability. He then showed how the Cadence 28nm unified digital flow addresses these issues. Areas of focus included multi-mode/multi-corner, on-chip variation (OCV), low power, physically aware synthesis, hierarchical design closure, and the new FlexModels technology.
The presentation also included several demonstrations. One showed how a new methodology, post-assembly closure, can close timing at the top level without requiring a lot of iterations between the block level and top level. Another illustrated lithography hot-spot prevention and in-design DFM signoff. A third showed how NanoRoute inserts double-cut vias and spreads wires to boost manufacturability.
Here's a listing of the currently available Technology on Tour On Demand sessions.
Highlights of new front-end design tools and features (including a new waveform viewer, Virtuoso Schematic Editor, and Virtuoso Analog Design Environment), and how to identify and analyze parasitic effects early.
Virtuoso Multi-Mode Simulation John Pierce, Product Marketing Director
Updates on the latest simulation capabilities including Virtuoso Accelerated Parallel Simulator distributed multi-core simulation mode for peak performance; a high-performance EMIR flow; Virtuoso Accelerated Parallel Simulator RF analyses; and an enhanced reliability analysis flow.
Virtuoso 6.1.5 - Top-Down AMS Design and Verification John Pierce, Product Marketing Director
Highlights of the latest in advanced mixed-signal verification methodology, checkboard analysis, assertions, and how to travel seamlessly among all levels of abstraction of the design.
Virtuoso 6.1.5 - Back-End Design Steve Lewis, Product Marketing Director
Highlights of the latest in constraint-driven design; Virtuoso Layout Suite; links between parasitic-aware design, rapid analog prototyping, and QRC Extraction; and top-down physical design: floorplanning, pin optimization, and chip assembly routing with Virtuoso Spaced-Based Router.
Virtuoso 6.1.5 - MS Design Implementation Michael Linnik, Sr. Sales Technical Leader
Highlights of the latest mixed-signal implementation challenges and solutions that link Virtuoso and Encounter technologies on the OpenAccess database, including analog/digital data interoperability, common mixed-signal design intent, advances in design abstraction, concurrent floorplanning, mixed-signal routing, and late-stage ECOs.
What's New in Signoff Hitendra Divecha, Sr. Product Marketing Manager
Highlights of standalone and qualified in-design signoff engines for parasitic extraction, physical verification, power-rail integrity analysis, litho hotspot analysis, and chemical-mechanical polishing (CMP) analysis.
Find out what's needed to be ready for 28nm design - process variation, power-performance-area optimization, DFM considerations, and more.
Trends in Digital Design (ECOs) Kenneth Chang, Sr. Product Marketing Manager
Find out what's needed to handle the increasing complexity of ECOs and their impact on schedule. Leverage a front-to-back automated ECO flow that can help you achieve a 3x gain in productivity and a much faster path to design tapeout.
Digital Design Technologies David Stratman, Sr. Product Marketing Manager
Highlights of new physically-aware technologies including physical synthesis and test; new constraint design capabilities including clock-domain-crossing (CDC) checks, low-power ATPG, and precision diagnostics flows; and low-power interoperability support.
Digital Implementation Technologies Wei Lii Tan, Sr. Product Marketing Manager
Highlights of new digital implementation technologies including design exploration with automatic macro-placement and flexible models; post-assembly closure for hierarchical implementation; new and improved optimization and clock-tree synthesis (CTS) during block implementation; and the latest mixed-signal capabilities across digital and custom design environments.
Digital Signoff Technologies Hitendra Divecha, Sr. Product Marketing Manager
Highlights of standalone and qualified in-design signoff engines for parasitic extraction, physical verification, timing, power-rail integrity analysis, litho
PCB Design Track
Allegro 16.5 - PCB Design Authoring (including FPGA-PCB co-design) Umar Shah, Sr. Sales Technical Leader
Technical presentation highlighting the newest capabilities for front-end PCB design, and a demo of FPGA-PCB co-design using Allegro FPGA System Planner.
Allegro 16.5 - Concurrent Team Design Authoring Umar Shah and Shawn Nikoukary, Sr. Sales Technical Leaders
Technical presentation and demo illustrating the concept of concurrent team design authoring; how it can encourage design reuse and make your design creation cycle shorter and more predictable.
Allegro 16.5 - Power Delivery Network Shawn Nikoukary, Sr. Sales Technical Leader
Technical presentation and demo on power delivery network analysis and how an integrated design and analysis solution, with no translation required, helps you converge on a working solution efficiently.
Allegro 16.5 - Design Planning Umar Shah, Sr. Sales Technical Leader
Technical presentation and demo on design planning to shorten the time to plan your interconnects and reduce the layer counts.
Allegro 16.5 - Signal Integrity Shawn Nikoukary, Sr. Sales Technical Leader
Technical presentation and demo on what's new in signal integrity. See advances in multi-gigabit analysis as well as DDR3 timing closure through integration with our technology partner's tool, TimingDesigner.