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You probably haven't read much about logic synthesis lately -- it's a mature technology that doesn't attract much attention. But that doesn't mean that new and exciting things aren't happening in synthesis and front-end design, as illustrated by presentations at a Synthesis Community Event held at Cadence Dec. 8.
The event included user presentations along with a Q&A panel discussion. I'll have more on that in a later post. This post focuses on a presentation by Adel Khouja, vice-president of R&D at Cadence, titled "Modern Synthesis Trends and Challenges for Today's and Tomorrow's Chip Design."
The talk focused on three trends - physical awareness moving upstream, power analysis and optimization, and increasing capacity requirements. Khouja began by noting that there has traditionally been a "very strong separation" between front-end and back-end design, but this is changing because physically-driven gate-level optimization has become necessary to close timing. Today, he observed, "physical knowledge is permeating logic synthesis" and is even moving up to architectural selection phases.
Khouja reviewed a number of ways in which front-end design and synthesis can become more physically aware. These include estimating and preventing routing congestion, using physical awareness during design for test (DFT), and restructuring and re-mapping logic based on physical knowledge. Suppose, for example, you want to find the best implementation for a multiplexer. "The point is, this is not a trivial decision, and you would want to base it on physical information," Khouja said.
As for power, Khouja noted that both dynamic and leakage power have been concerns for many years, and neither one is going away - in fact, with process advancements now promising to reduce leakage power, dynamic power is re-emerging as a serious concern. There is also increasing interest in bringing power estimation up to the architectural level, he noted. What won't be changing soon, he said, is the focus on power as something almost as critical, if not more critical, than timing.
Khouja said that a "holistic" approach to power intent specification is vital, so that power intent can be conveyed and optimized throughout the flow. He predicted more cooperation among EDA vendors around the area of power intent.
Capacity has always been a challenge for synthesis, and top-down methodologies have increased memory requirements and run times. Further, some designs are already at the 20-50 million gate equivalent range with future designs surpassing 100 million gates. Controlling capacity and run time "is an exciting area and our team is working on this," Khouja said. One way to improve capacity is through multi-threading and shared memory, and another is distributed processing.
Physical Synthesis or Physically Aware?
An audience member asked if "physically aware" synthesis is the same thing as "physical synthesis." Khouja replied that "physical synthesis is a very vague and broad term. I think we're going beyond that...we're talking about physical aware logic synthesis. We're taking placement, congestion, blockages, and the clock tree, and moving it into the front end. What you're likely to see is really a merging of the front end and the back end over time."
Synthesis is a technology that is absolutely central in the IC design flow. It's good to know that the technology is still evolving and improving.