Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
One of the big advantages of 3D-ICs with through-silicon vias (TSVs) is the potential for much faster memory bandwidth compared to conventional 2D ICs. That's why the emerging JEDEC wide I/O mobile DRAM memory standard, which takes full advantage of 3D die stacking to provide significant power and performance gains, is a key driver for the move to 3D-ICs. A timely update on wide I/O was presented Dec. 12 at the Global Semiconductor Alliance (GSA) 3D-IC Working Group meeting in Santa Clara, California.
I say "timely" because the speaker, Ken Shoemaker, vice-chair of the JEDEC JC-42.6 committee, noted that the initial wide I/O specification has been approved by the JEDEC board of directors and "should be published any day now." Shoemaker provided some background about the specification, detailed what it does and doesn't cover, and talked about thermal and test challenges and solutions.
JEDEC describes wide I/O as "a breakthrough technology that will meet industry demands for increased levels of integration as well as improved performance, bandwidth, latency, power, weight and form factor. Wide I/O mobile DRAM memory uses chip-level three dimensional (3D) stacking with through silicon via (TSV) interconnects and memory chips directly stacked upon a system on chip (SoC). Wide I/O is particularly suited for applications requiring increased memory bandwidth up to 17GB/second, such as 3D gaming, HD video, simultaneously-running applications, etc."
Wide I/O defines four memory channels each 128 bits wide, providing a 512-bit wide interface to memory. The interface supports a single data rate of 266M transfers/second, and channel bandwidth of 4.26GB/second, or total bandwidth of 17GB/second (up from 12.8GB/second targeted earlier in the standards effort). The goal of wide I/O, Shoemaker noted, is to provide "double the bandwidth at the same power, or cut power in half at the same bandwidth" compared to LPDDR2 and LPDDR3. "It lets you get smaller form factors and lower power, so what's not to like?"
What the Spec Covers
The wide I/O specification defines the logic/memory interface (LMI). Two JEDEC committees have contributed to the wide I/O specification. While the JC-42.6 (low power DRAM) group has focused on functional aspects of the device, the JC-11 (mechanical standardization) group has focused on mechanical aspects of the chip, such as pad dimensions, tolerances and locations. The mechanical interface is called a micropillar gate array (MPGA).
The specification also standardizes the following:
Thermal integrity is obviously a big concern for 3D-ICs, and Shoemaker went into some detail in this area. He explained that the DRAM self-refresh rate varies with temperature, and DRAM chips expect a uniform temperature. However, logic chips generate non-uniform hot spots as various activities take place, such as watching a video. Therefore, the logic chip will determine the temperature delta between the memory hot spot and the location of the thermal sensor on the DRAM. Wide I/O seeks to standardize locations for memory thermal sensors, but the accuracy of the sensor and the algorithm it uses is a proprietary matter.
Here are some more details on the 4-channel LMI:
"You have to do the math to figure out how much this is going to change your die area," Shoemaker said.
What the Spec Doesn't Cover
Shoemaker presented a long and important list of items the wide I/O spec does not cover. This includes any internal aspects of the memory chip or memory stack. The spec doesn't mandate the interconnect method between memory and logic chips - it could be face-to-face, side-by-side with interposer, or stacked memory on top of logic. The exact mechanical placement of the interface on the logic or memory chip is up to the designer, although "we presume it's in the center of the memory chip." Dimensions and placement of TSVs are not specified.
Shoemaker also noted that discussions are underway about the next generation of wide I/O. There are proposals for significantly higher bandwidth, and explicit support for 2.5D assembly. There's also a JEDEC High Bandwidth Memory group that is leveraging some of the wide I/O work, but this group is targeting high-performance applications. Wide I/O is more focused on mobile devices and tablets and other power-sensitive applications.
Wide I/O Gets Real
On Dec. 13, at the RTI 3-D Architectures for Semiconductor Integration and Packaging conference in Burlingame, California, representatives of CEA-LETI and ST-Ericsson described the development of a three-die stack with wide I/O memory and two logic dies. This 3D-IC is the result of collaboration between these two organizations and Cadence, which provided the design tools and the wide I/O controller IP for the project. A previous blog post has details.
In March 2011, Cadence announced the first commercial wide I/O memory controller IP solution. As described in a previous blog post, the Cadence wide I/O offering includes a configurable memory controller, PHY (physical layer), and verification IP. Cadence also provides a comprehensive methodology and tool support for 3D-IC/TSV design, including IC/package co-design, 3D-aware floorplanning and routing, extraction, thermal analysis, test, and custom/analog design as well as digital. That flow is described in a previous blog post.
In summary, wide I/O presents a compelling new technology for a new generation of mobile, high-bandwidth, low-power devices. The emerging JEDEC specification will help drive this technology and bring 3D-ICs with TSVs into the mainstream.
Shoemaker's presentation is available at the GSA web site.