Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
As system complexity grows and semiconductor process nodes shrink, EDA industry standards are more important than ever. With today's time-to-market pressures, the last thing you'd want to do is waste time due to incompatible formats, tools or methodologies. Fortunately, 2011 was a productive year for EDA standards developments and 2012 is looking promising as well. This blog post summarizes some key developments.
Perhaps the biggest standards news of the year was the merger of Accellera and the Open SystemC Initiative (OSCI) into the Accellera Systems Initiative, completed Dec. 5, 2011. This follows the 2010 merger of the SPIRIT Consortium into Accellera. As I noted in a blog post earlier this month, the stage is now set for a unified, front-end EDA standards effort that cuts across multiple levels of abstraction. Looking forward to 2012, there are many opportunities for convergence among standards efforts such as Accellera's Universal Verification Methodology (UVM), IP-XACT from the SPIRIT Consortium, and OSCI SystemC and Transaction-Level Modeling (TLM-2.0).
While the Accellera Systems Initiative concentrates on front-end standards, the Silicon Integration Initiative (Si2) is traditionally focused more on the back end. A major Si2 development in 2011 was the release of Common Power Format (CPF) 2.0, an update that facilitates interoperability between CPF and the IEEE 1801 Unified Power Format (UPF), and the contribution of CPF 2.0 to IEEE 1801. Cadence, the originator of CPF, is now actively participating in IEEE 1801. An October blog post has further information about Si2's work in power standards.
Here are updates on some other key standards efforts (not necessarily in order of importance). Cadence is placing a strong priority on standards and is actively involved in most of the efforts listed below. Thanks to various committee chairpersons for helping with these updates.
ACCELLERA SYSTEMS INITIATIVE
UVM - On Feb. 18, 2011, Accellera approved the long-awaited UVM 1.0 as a new industry standard. Currently based on SystemVerilog, UVM provides a standard methodology so that verification IP and testbenches can be reusable and interoperable in different simulation environments. A bug fix release, UVM 1.1, was subsequently issued, and a more substantial new release, UVM 1.2, is expected in 2012.
SystemC - Before the merger with Accellera, OSCI working groups made continued progress in 2011 in defining a synthesis subset, analog/mixed-signal extensions, and model configuration and control. While the SystemC language itself is now under IEEE 1666, OSCI worked on a proof-of-concept reference model. Six OSCI SystemC working groups are now part of the Accellera Systems Initiative.
Unified Coverage Interoperability Standard (UCIS) - In 2011, the UCIS committee completed the technical work for a version 1.0 draft of a standard that will foster interoperability between verification coverage metrics from different sources. The standard is heading for approval in early 2012.
Standard Co-Emulation Modeling Interface (SCE-MI) - Accellera released version 2.1 of the SCE-MI standard, which added a "pipes" interface to the previous methods of communicating between software execution and hardware acceleration. Additional capabilities are planned for 2012 including SystemC and SystemVerilog interfaces.
IP-XACT - This standard provides metadata that documents the characteristics of silicon IP. In 2011 the working group captured new requirements and defined a process for the release of standard extensions.
IEEE WORKING GROUPS
IEEE 1666 (SystemC) - The first IEEE revision of SystemC in six years, IEEE 1666-2011, was released in November. The language reference manual includes the TLM modeling specifications from OSCI; it also adds process control statements, based on technology developed by Cadence.
IEEE 1800 (SystemVerilog) - A new version of the SystemVerilog standard is expected in 2012.
IEEE 1801 (Unified Power Format) - As noted above, Cadence has joined this working group, which now has access to CPF 2.0. A new revision, IEEE1801-2012, is planned for 2012. Looking further out, a "UPF 3.0" release is expected to include concepts from OpenLPM and CPF.
IEEE 1647 (e language) - IEEE 1647-2011 was published in August 2011 with a number of language updates. The working group is awaiting feedback on the standard and will start an open period for new contributions in mid-2012.
IEEE 1734 (IP quality) - The IEEE approved IEEE 1734-2011, a standard for IP quality, in June and released it in September 2011. The group is looking for industry feedback before undertaking any revisions or enhancements.
SILICON INTEGRATION INITIATIVE
OpenAccess Coalition - In 2011, a new OpenAccess release included support for 28nm constraints and compressed databases. OpenAccess scripting language bindings were released. A 2012 OpenAccess release will include scratch designs and other functionality and performance improvements.
DFM Coalition - The OpenDFM 1.1 physical verification standard was released in 2011, including electro-static discharge checks, latch-up checks, edge checks, and new targeting functions for manufacturability. In 2012, OpenDFM 2.x will include DRC+ and other enhancements.
OpenPDK (Process Design Kits) - Work has started on the Open Process Specification, which will include a symbol standard, a design parameter standard, a callback standard, and other design rules.
Low Power Coalition (LPC) - CPF 2.0, released in 2011, facilitates interoperability with IEEE 1801. Updated power modeling standards are expected in 2012.
Open3D (3D-ICs) - This new effort formed working groups in 2011 and is expected to release standards in 2012 defining power distribution network across the die of a 3D stack, thermal design and analysis of an entire 3D stack, and expression of design constraints into and out of the pathfinding and floorplanning phases of the design process.
It's a long list and it's not a complete list - many EDA standards efforts are ongoing. Here's a big end-of-year "thank you" to all those individuals who are donating their time to making these standards happen.