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Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using the Common Power Format (CPF). The new flow provides many advantages compared to the traditional bottom-up, single-mode synthesis approach.
This was one of three user presentations at the event, which also featured a panel session involving the presenters. All of the user presentations focused on low-power design, and power was a prominent topic at the panel discussion. A previous blog post includes a report of the panel.
In a memory controller, Borbely-Bartis noted, sub-modules may have different timing requirements, and there could be multiple power domains. With bottom-up synthesis, however, sub-module I/O delay is budgeted for the worse case, and as a result some paths are over-constrained. Single-mode synthesis constrains the top level in order to satisfy the worst-case mode. Power structures including isolation cells (ISO) are added later, power shutoff (PSO) simulation is delayed until the netlist is available, and design for test (DFT) structures are also added late in the flow.
The traditional flow looks like this, where A1 and A2 are sub-modules and LEC is logic equivalence checking:
The new, multi-mode flow (below) starts with a CPF file that describes power intent and a power-aware simulation. Top-down synthesis makes module-level standard delay format (SDF) files unnecessary. The top level is constrained for each mode, and power structures and DFT are added during synthesis. "We provide multiple SDC [standard design constraint] files for the different modes," Borbely-Bartis said.
Borbely-Bartis showed how the CPF file defines libraries and cells, creates power domains and modes, establishes isolation rules, and specifies power management cells including those for ISO and PSO. He noted that the CPF file allows for RTL PSO simulation, permitting early detection of possible power problems. When a PSO signal is asserted, the signals inside a shut-off domain are automatically forced to "X" (unknown) states. Thus, no testbench modification is needed for PSO support.
Each functional mode is described in a separate SDC file. There are also dedicated modes for scan and memory built-in self test (BIST).
As a result of the new flow, the design is not over-constrained, and ISO and PSO cells are automatically inserted. The final LEC is automated and driven by the CPF file, making LEC power-aware. In the old flow, Borbely-Bartis noted, die size may increase and overall timing may suffer.
Borbely-Bartis uses tools including the Cadence Encounter RTL Compiler, Conformal LEC, Conformal LP, Incisive simulation, and the Encounter Digital Implementation System. All these tools read CPF. PSO simulation with RTL, he noted, "allows early detection of most power issues. It also allows us to do more testing. Whatever you find, fixing RTL is much easier than reporting ECOs later."
Very novel concept with the help of CPF format and power domain. Most of the post P&R pain points can be brought upfront at the front-end stage thus increasing TAT of the overall flow and chip reliability and manufacturability.