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Ten Cadence papers planned for the upcoming SPIE Advanced Lithography conference, set for Feb. 12-16 in San Jose, California, demonstrate recent R&D developments in both "design side" design for manufacturing (DFM) and the computational lithography that takes place during the manufacturing phase. The papers will be given Feb. 14-16 and are all co-authored with customers or partners.
According to Manoj Chacko, product marketing director at Cadence, "design side" DFM includes such topics as layout-dependent effects (LDE) and electrical variability for custom and digital designs, pattern matching based in-design DFM signoff, in-design litho hotspot repair, in-design chemical mechanical polishing (CMP) analysis, and hierarchical closure for IP blocks.
As reflected in the SPIE 2012 papers, Cadence R&D efforts in DFM have focused on quantifying the impact and minimizing the differences caused by LDE, building the yield detractor pattern infrastructure for leveraging pattern matching for litho signoff, estimating CMP effects for IP blocks, and allowing signoff-quality analysis during the design phase (see my earlier post on in-design DFM signoff here).
Computational lithography, which takes place after design rule checking (DRC), includes double patterning, source-mask optimization, and optical proximity correction (OPC) including OPC verification. Chacko said that Cadence is using "third generation" inverse lithography techniques to boost OPC, providing high-capacity full-chip dense OPC verification, and offering accurate model calibration. Cadence also does source and mask optimization concurrently.
The ten Cadence co-authored papers are listed below. Note that SPIE is organized into different "conferences" in such areas as extreme ultraviolet lithography (EUV), metrology, advanced lithography, DFM, and advanced etch technology. A complete SPIE program is located here. To read abstracts of these papers, click here.
SPIE Papers - Design Side DFM
Electrical design for manufacturability and layout-dependent variability hotspot detection flows at 28 nm and 20 nm Paper 8327-40 of Conference 8327Date: Wednesday, 15 February 2012Authors from Cadence and GLOBALFOUNDRIES Singapore
Analysis of layout-dependent context effects on timing and leakage in 28 nm Paper 8327-17 of Conference 8327Date: Wednesday, 15 February 2012Authors from Cadence and Freescale
CMP effect due to perimeter: a perimeter drive dummy fill optimization approach Paper 8327-37 of Conference 8327Date: Wednesday, 15 February 2012Authors from Cadence and Samsung
In-design process hotspot repair by pattern matching Paper 8327-27 of Conference 8327Date: Thursday, 16 February 2012Authors from Cadence and Samsung
SPIE Papers - Computational Lithography
Model calibration and full-mask process and proximity correction for extreme-ultraviolet lithography Paper 8322-55 of Conference 8322Date: Thursday, 16 February 2012Authors from Cadence and Applied Materials
Self-aligned double patterning (SADP) compliant design flow Paper 8327-5 of Conference 8327Date: Wednesday, 15 February 2012Authors from Cadence and GLOBALFOUNDRIES
Free form source and mask optimization for negative-tone resist development for 22nm node contact holes Paper 8326-31 of Conference 8326Date: Wednesday, 15 February 2012Authors from Cadence, Applied Materials, and FUJIFILM Electronic Materials)
Lithography target optimization with source-mask optimization Paper 8326-100 of Conference 8326Date: Wednesday, 15 February 2012Authors from Cadence and GLOBALFOUNDRIES
Cadence will be holding private briefings and demonstrating DFM and lithography solutions Feb. 14 and 15 for advanced-node ICs using custom/analog (Virtuoso) and digital (Encounter) environments. Further information is located here.