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A free lunch, a 50% off deal on a new verification book, and a chance to hear about real-world experiences in low-power verification -- it's all happening Tuesday Feb. 28 at the DVCon 2012 conference in San Jose, California.
The Cadence-sponsored lunch, which runs from 12:30 pm to 2:00 pm, is titled "Earn Your Degree in the Low-Power Arts and Sciences." As the event abstract describes, the "science" represents the tools that process the power format files, while the "art" is the creation of a power-aware verification methodology. This methodology makes every verification regression power-aware, and expands the verification focus to include low-power assertions, formal techniques, and a low-power verification plan.
The lunch will feature three user panelists and two EDA vendor panelists as follows:
Pete Hardee of Cadence helped organize the event. "We'll be trying to get a sense of real-life experiences of the investment required, difficulties introduced, and benefits of applying low-power techniques, with a particular focus on power-aware verification," he said.
The 50% discount alluded to above applies to the new Advanced Verification Topics book, which shows how the Universal Verification Methodology (UVM) can be applied to mixed-signal, low power, and multiple languages. You can read my blog review about the book here or go directly to the Cadence.com description and ordering information here. (Actually, anyone buying the book at Lulu that week will get the discount.)
There's much, much more happening at DVCon. You can read about Cadence activities and papers here and you can find a complete agenda listing, along with registration information, at the DVCon web site. The conference runs Feb. 27-March 1 at the Doubletree Hotel in San Jose.
See you at the "power" lunch!