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Realizing that high-performance (GHz range), high capacity (100M+ instances), and 20nm digital IC designs need new tools and methodologies, Cadence today (March 5, 2012) is announcing Encounter Digital Implementation System 11.1. Here's an inside look at three technology innovations that make it possible - a new optimization engine, a new abstraction technology, and a correct-by-construction approach to 20nm double patterning.
The new digital flow was developed in cooperation with foundries, IP providers, and customers. It recognizes what we all know -- that IC designs are becoming more complex and faster to empower a new world of mobile devices, servers, smartphones, tablets, intelligent automobiles, and more. Advanced ARM processors such as the Cortex-A9 and Cortex-A15 are gaining ground. Increased functionality and performance needs are leading many device manufacturers to adopt 20nm, which brings about additional challenges such as double patterning.
Information presented in this blog post was provided by Limin He, vice president of R&D at Cadence, and Rahul Deokar, product marketing director for digital implementation. While this blog post focuses on physical IC design, Encounter 11.1 also brings new technology to front-end design, and that will be the subject of a subsequent post.
GigaOpt Pushes Design into GHz Range
One Encounter 11.1 technology innovation is a new RTL-to-GDSII core optimization engine called GigaOpt that results in optimal performance, power and area. What is most distinctive is that GigaOpt provides a common optimization engine across IC physical design, bringing physical-aware synthesis and physical optimization together. This leads to improved correlation between the front-end design and back-end implementation, and significantly faster design convergence, Limin He said.
GigaOpt provides better quality of results with a 30% full-flow runtime speedup for design closure on a single CPU. It provides a substantial boost in turn-around time because it has a multi-threaded architecture that can effectively use multi-core computers, and scale run times upwards as more cores are added. Turn-around time gains of 1.5-2X have been demonstrated on 4 CPUs running real customer designs, according to Deokar.
The diagram below shows what GigaOpt includes. An advanced analysis engine (AAE) is at its core. GigaOpt today works in three stages - after placement, after clock tree synthesis, and after routing. In addition, GigaOpt integrates the new Clock Concurrent Optimization (CCOpt) technology that unifies clock tree synthesis with physical optimization, resulting in 10% improvements in design performance and total power and a 30% reduction in clock power and area.
GigaFlex Enables High-Capacity Designs
GigaFlex is a new abstraction technology that facilitates "giga-scale" design closure. It is based on a simple idea - that you model intelligently what is needed at a given phase of the design cycle, and let the model become more accurate as the design proceeds. As compared to traditional methods that are limited to logical and electrical modeling, another difference is that GigaFlex brings in physical/congestion modeling early on in the flow resulting in faster design convergence, according to Deokar. GigaFlex will dynamically adjust the content and accuracy of models during the physical design process in order to provide optimal capacity and turn-around times for giga-scale designs of 100M instances or more.
As shown below, GigaFlex works on three levels. During prototyping - a step that includes floorplanning, design exploration and planning - GigaFlex uses FlexModels and achieves a 10X speedup over previous methods. FlexModels, for instance, retain registers, module boundary logic, and hard macros. Combinational logic is abstracted into "Flex Fillers," which model full netlist connectivity and area.
While accurately modeling area, congestion and timing, FlexModels reduce the netlist by up to 95%, leading to higher capacity and faster turn-around times. During top and block-level implementation, GigaFlex uses FlexILMs, and during post-assembly closure, GigaFlex uses FlexViews to enable concurrent top-and block hierarchical implementation and closure, reducing iterations and total design cycle time.
Correct-by-Construction 20nm Design
Both GigaOpt and GigaFlex should prove very useful for 20nm designs, given that nearly all will feature high capacity and many will run in the GHz range. Beyond GigaOpt and GigaFlex, Encounter Digital Implementation System 11.1 also provides a unified 20nm digital implementation and signoff flow.
To support 20nm, Cadence engineers re-architected the router so it supports dozens of complex new layout rules without sacrificing run time or density. Additionally, the new Encounter release fully supports double patterning, which uses extra masks to overcome the limits of existing lithography systems. This affects not only the router, but also placement, extraction, and physical verification -- basically, the whole physical design flow has to be double-patterning aware. Also, the new FlexColor correct-by construction double patterning implementation engine allows metal shapes in the design color to be assigned in real time, allowing more flexibility towards implementing a double-patterning correct design.
What really stands out, Deokar said, is that Cadence uses a correct-by-construction approach to support double patterning. That's very different from a traditional post-processing strategy, which tries to fix things at the end of the design cycle and typically results in a lot of iterations. Correct-by-construction also provides a better way to control congestion.
Cadence has been working with major foundries on 20nm support over the past few years and has announced 20nm tapeouts with Samsung and TSMC. Further information about Encounter 11.1 is available here.