Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Double patterning will be an essential lithographic technique for ICs at 20nm and below. The more we can understand it, and quantify its impacts on the design flow, the easier it will be to adopt. A good step towards that understanding was taken at CDNLive! Silicon Valley 2012 (the recent Cadence user group meeting) where Lars Liebmann, distinguished engineer at IBM and an industry expert on lithography and design rules, presented a paper that provided a detailed update on double patterning at 20nm and 14nm.
The paper, titled "Quantifying the Design Impact of Double Patterning for the 20nm and 14nm Technology Nodes," was co-authored with Paul Gutwin of Cadence. The paper presents a scaling roadmap, shows how remaining technical challenges in EUV make it difficult to predict the exact date of its availability for volume manufacturing, offers a tutorial that contrasts two types of double patterning, and presents the results of routability experiments run using the Cadence Encounter Design Implementation System.
Liebmann first showed a scaling roadmap that illustrates how far the 20nm and 14nm nodes are operating below the limits of existing 193nm optical lithography, which can squeeze out a 40nm half-pitch at best. It also shows how far these nodes are above the limits of EUV, which has a wavelength of just 13.5nm. Why do we care now? Liebmann noted that we need to have the capability to make integrated wafers in significant volumes several years before the manufacturing ramp.
Don't Hold Your Breath for EUV
Liebmann then offered a detailed look at EUV. Before this presentation, I had not realized how exotic and complex this technology is. Clearly the EUV 13.5nm wavelength provides much better resolution than 193nm optical lithography - but it comes at a cost. While optical lithography uses a laser source, EUV uses plasma. Instead of running in ambient air, EUV requires a vacuum. Instead of photons, the EUV exposure reaction system uses secondary thermal electrons.
The way EUV works sounds a bit like science fiction. It starts with a microscopic drop of tin that falls through a vacuum, and is then zapped by a laser. This reshapes the drop so it has more surface area. Then the EUV system explodes the droplet, giving off a few photons at 14nm, along with other wavelengths that need to be filtered out and debris. Behind this explosion is a very expensive mirror that reflects the 14nm wavelength photons.
Here are a few other facts about EUV:
Small wonder, then, that EUV development has been ongoing for three decades now and the technology is still several years away. Even so, IBM is continuing its EUV development work with a goal to have the technology ready for insertion in the wafer development flow by the end of 2013. Liebmann said the original experimental EUV machine installed in Albany Nanotech in 2006 "looked like something NASA would send to Mars."
If EUV is delayed, Liebmann said, massively parallel e-beam lithography may be used at 10nm and below. But he doesn't think it will be ready at 14nm.
Two Types of Double Patterning
So we're well below the limits of optical lithography, and EUV will be too late - thus, Liebmann argued, double patterning will be essential at 20nm and 14nm. He presented two types of double patterning - "pitch split" (also called litho-etch litho-etch, or LELE) and "sidewall image transfer" (also called self-aligned double patterning or SADP). These are different techniques with various tradeoffs. The bottom line is that pitch split is simpler, while sidewall image transfer gives better resolution.
Double patterning splits a pattern that could not otherwise be printed into two separate masks. As shown below, the way pitch split does this is fairly intuitive. Following layout decomposition and coloring, half the patterns go on the first mask, and half go on the second mask. With sidewall image transfer, however, there's a much more complex process that includes building relief features onto the wafer, depositing sidewall spacers onto these relief features, removing relief features, adding dielectrics to open areas, and finally removing dielectrics everywhere except under the sidewall. One advantage is that there is less intra-level overlay error compared to pitch split.
It's important to understand these techniques because they are implemented differently, and involve different design rules. For example, color-dependent spacing rules are more complex in sidewall image transfer than in pitch split. On the other hand, overlay errors cause more serious problems with pitch split. Sidewall image transfer does not allow the router to fix problems by "stitching" traces, while pitch split allows a limited stitching capability.
Liebmann said that "sidewall image transfer has a more complicated rule set, but it gets closer to the ultimate resolution limit we'll enjoy with EUV." How much closer? The chart below gives an idea.
Cadence and IBM worked together on experiments that quantified the impact of double patterning on routability. These experiments used an experimental design created with a 12-track IBM 14nm library. The routing included layers M1 through M5, but only M2 and M3 were double patterned. There were three routing scenarios:
The metrics drove routing to the same design quality for the 3 styles, and then measured via count, wire length, and distribution of jogs by the number of tracks jumped. Liebmann noted that both the process and the router are still evolving.
The experiments explored placement density between 60% and 90% in 5% increments. While the uncolored design became unroutable between 85% and 90% density, the colored designs became unroutable between 80% and 85%. Thus, the density cost of putting double patterning into the router appears to be around 5%.
The experiments showed about a 20% increase in via counts (for all layers) for colored unidirectional, and a 15% increase in via counts for colored bidirectional, compared to the baseline uncolored bidirectional. Wire length increases were a few percent for double pattern routing, with colored bidirectional routing showing smaller increases.
Thus, unidirectional routing has a slightly larger via and wire length penalty than bidirectional routing, leading Liebmann to conclude that there is sufficient motivation to solve the tougher bidirectional color correct routing problem rather than rely on unidirectionality to simplify double patterning aware routing. On the other hand, the analysis of jog-height distribution in the two bidirectional layouts indicated that the benefit of forcing routers to understand and exploit stitching may be very marginal.
"The experiments I shared with you today showed first and foremost that Cadence was able to embed two-color mapping into their router, which is a very important first step," Liebmann concluded. "We just need to keep tweaking to bring down the via count and wire length increase a little bit."
Liebmann offered a tutorial on double patterning in a video presentation at the Design Automation Conference 2011. CDNLive! Silicon Valley 2012 proceedings will be available here for conference attendees.