Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Network processing chips are tough to design. They're big, they're fast, and they have to minimize power consumption. At CDNLive! Silicon Valley 2012 (the Cadence user group conference) Ranjit LoboPrabhu, physical design manager at Netronome Systems, shared some ways his company is going "green" with its network processors, and offered a quantitative evaluation of the clock current optimization (CCOpt) technology now provided by Cadence.
Acquired from Azuro last year, and now available with the Encounter Digital Implementation System 11.1, CCOpt runs clock tree synthesis (CTS) concurrently with placement and physical optimization. It uses a "timing window driven" engine to optimize timing paths and clocks simultaneously. The technology promises improvements in overall design performance and power, as well as a reduction in clock area and power. At Netronome, LoboPrabhu put those claims to the test. (For further information on CCOpt, see references at the end of this post).
LoboPrabhu's paper was titled "Being Green -- What Good Design and CCOpt can do to Reduce Power." In addition to talking about CCOpt, LoboPrabhu offered some general tips for low-power system-on-chip (SoC) design. At the top of the list is setting a realistic timing goal. How can this be done? One way is to look at the distribution and sizes of cells. Another is to benchmark the design at different frequencies and observe the resulting power.
CCOpt Results from Two Designs
In an interview following his presentation, LoboPrabhu noted that Netronome used two "production worthy" designs to evaluate CCOpt. Design 1 was a memory controller block that was minimally optimized, and Design 2 was a processor block that was thoroughly hand-tuned.
With a traditional approach aimed at "balancing" clocks, CTS runs separately from optimization. Even if a designer converges timing in synthesis, LoboPrabhu said, "things don't scale exactly as they did during synthesis because you have parasitics and congestion. New critical paths are introduced and convergence is a challenge."
CCOpt combines CTS with optimization, and "there is absolutely an advantage in doing that," LoboPrabhu said. "You get the ability to optimize a whole design together, and you aren't concentrating on only designing a clock tree and then trying to retrofit that into a design." CCOpt, he said, "has an idea of the whole design space and can skew the clock tree so it doesn't violate any of the setup and hold constraints."
And the results? On Design 1 (1.5M instances) CCOpt demonstrated a 29% power savings and a 10% improvement in timing. This is for the entire block, not just the clock tree. With Design 2, which was better optimized to begin with, CCOpt increased the timing margin by 80 ps, about a 7% to 8% improvement, and provided an additional 5% power savings. LoboPrabhu noted that "everything was very timing critical in this design, it had been manually optimized, and even in this tight space CCOpt was able to demonstrate good numbers."
Netronome started using clock concurrent optimization when it was provided by Azuro. At the time, some file format translation was needed. Now that it's integrated into Encounter 11.1, LoboPrabhu said, "it's a breeze. It's one command and it does all the steps you had to do before." He also likes its clock tree visualization capabilities. In the future, he'd like to see the technology extend into routing.
Low Power Tips
In his CDNLive! presentation, LoboPrabhu shared these tips on conserving power:
Why all the concern about low power? Power consumption has become a big concern for data centers as more and more data moves into the cloud. Power constraints on chips and systems that go into data centers are becoming more and more stringent. "Conserving power positions us better to compete in the marketplace," LoboPrabhu said.
Thus, being "green" has a direct impact on Netronome's bottom line.
CDNLive! Silicon Valley 2012 proceedings will be available here for conference attendees.
Further Information on Clock Concurrent Optimization
Industry Insights blog: Why Cadence Bought Azuro - A Closer Look
Industry Insights blog: Q&A: Former Azuro CEO Explains Clock Concurrent Optimization
Chip Design Magazine article: Clock Concurrent Optimization Reshapes IC Physical Design Flow