Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
What's needed to bring 3D-ICs with through-silicon vias (TSVs) - or 2.5D ICs with silicon interposers - into the IC design mainstream and volume production? That question resonated through a day-long session on 3D-ICs at the Electronic Design Processes Symposium (EDPS) April 6, 2012 in Monterey, California.
EDPS is an IEEE sponsored workshop that brings together some of the key movers and shakers in the EDA industry for two days of thought-provoking presentations and animated discussions. In addition to 3D-ICs, this year's topics included FPGA systems-on-chip, system-level design, cloud computing, and low power design, in addition to 3D-ICs. Corporate sponsors included Cadence, Mentor Graphics, and Synopsys.
The 3D-IC session was organized by Herb Reiter, president of eda2 asic and chair of the Global Semiconductor Alliance 3D/TSV Working Group. It began with an hour-long keynote by Riko Radojcic, director of engineering at Qualcomm, followed by a shorter talk by Arif Rahman, product architect at Altera. Several EDA vendor talks (including two from Cadence) followed, along with a panel discussion. This blog post focuses on the presentations by Radojcic and Rahman, and a future post will review the panel.
Qualcomm's Riko Radojcic presents at EDPS 2012
Radojcic noted that 3D-ICs are "almost getting mainstream" and are moving along the adoption curve (depicted on the slide shown above). He talked about the many types of 2.5D and 3D-ICs that are already in design or production by memory, foundry, CPU/GPU, FPGA, and mobile providers. Qualcomm is investigating stacked dies including memory and logic. Why? As 2D scaling gets more expensive, Radojcic said, 3D "seems like a very good opportunity."
One example of the value proposition of 3D-ICs comes from wide I/O memory. Radojcic noted how wide I/O provides much better power efficiency, and much more scalability to higher bandwidths, than LPDDR3 memory - and the only way to effectively use wide I/O is stacked die. He also noted that stacking one chip on top of another gives you a "kick in performance" about equal to moving down one process generation. Which is cheaper? It depends on when and what you design, but a 3D-IC with TSVs could potentially be more cost-effective than moving down to another process generation.
Most of the process issues are conceptually ironed out, Radojcic said. The industry knows how to make holes, thin dies, and stack wafers. The remaining issues need to be sorted out with volume manufacturing. He also emphasized that EDA tools and standards are needed to leverage the advantages of 3D-ICs. Specifically, he called for the following capabilities:
An FPGA Perspective
Arif Rahman then spoke about what Altera needs from the EDA community for its internal 3D-IC design work. Altera is interested in 3D technology because of the potential for higher bandwidths, faster time to market, and the potential to integrate FPGA fabrics with ASICs, ASSPs, CPUs, memory, and other functions. In March 2012, Altera and TSMC announced a heterogeneous 3D IC test vehicle.
Rahman traced out a desired 3D EDA flow very similar to what Radojcic presented. He also cited the need for standards. However, Rahman noted, Altera's challenge is somewhat different from that of SoC or ASIC providers, because an FPGA is 70-90% custom design.
Rahman's suggested flow starts with Pathfinding and planning in order to evaluate stacking configurations and chip-package interactions. It then moves on to physical design implementation including floorplanning, TSV and microbump planning, and 2.5D/3D die stack configuration. This step is followed by performance validation for signal integrity, power, thermal, timing, and other criterion. Finally, signoff verification needs to include thermal, mechanical and power considerations in addition to traditional design rule checking.
"One thing unique to 3D is the thermal aspect. You are going from a die that is 500 to 700 microns thick and thinning it to 50 or 100 microns. So thermal aspects are much more pronounced than with 2D ICs and you have to consider them much earlier in the design flow," Rahman said. He cited the need for calibrated models for electrical, thermal, and thermo-mechanical analysis.
So what's the bottom line? Making money, of course. "We see 3D as an enabler to provide more system level capabilities," Rahman said. "That will help companies move up the value chain. And the higher you move up in the value chain, the higher the business opportunity."