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It's time to get to work if we want to bring 3D-ICs with through-silicon vias (TSVs) into the semiconductor design mainstream. What ecosystem support is needed in the short term, medium term, and long term to make this new technology successful? That's the question that was put to a panel of 3D-IC experts at the recent Electronic Design Processes Symposium (EDPS) April 6, 2012 in Monterey, California.
The panel was titled "The Path to the 3D Ecosystem - Short, Medium, and Long Term." It was the conclusion of a day-long session on 3D-ICs that also included user perspectives from Riko Radojcic of Qualcomm and Arif Rahman of Altera; a talk by Marc Greenberg of Cadence on the wide I/O DRAM standard; and presentations by Mentor and Cadence on 3D-IC test (see links at end of this post for previous blog coverage of the day).
The panel was moderated by Steve Leibson, marketing director at Cadence and author of the EDA360 Insider blog. Panelists were as follows, shown left to right in the photo below:
The panel discussion covered topics ranging from tungsten vias and glass interposers to EDA tool support and standards. Panelists were optimistic about 2.5D (silicon interposer) and 3D (stacked die) technologies, but were also realistic about current challenges and unresolved issues. All in all, it was an incredibly informative panel packed with information you're not likely to hear anywhere else. Here are some highlights from the opening presentations.
Phil Marcoux - The Truth About Copper
Phil Marcoux, a pioneer of surface mount technology, is deeply involved in the manufacturing side of 3D-IC technology. "Designing these 3D and 2.5D assemblies is a team sport and you need a lot of players," he said. These include device suppliers, interposer designers and suppliers, assemblers, material suppliers, and (tongue in cheek) an understanding pharmacist or beverage supplier.
I think he surprised some people in the audience -- myself included -- by noting that the TSVs in production today are actually tungsten vias. A typical TSV diameter is 5 microns, and manufacturing copper vias that small is difficult and costly. "There's a group of us promoting the idea of dual-purpose vias -- tungsten for the small vias, and the larger sizes can use thermal copper vias."
Marcoux also announced the formation of a 2.5D/3D Council along with Herb Reiter and Dieter Bergman, a veteran of the IPC standards organization.
Herb Reiter - No Free Lunch
"There is no free lunch, and I'm sure a lot of us are realizing now that there is a lot of work to be done to enjoy 3D benefits," Reiter said. In the short term, he said, EDA providers should agree on data exchange formats, and work with materials and equipment providers to bring accurate models into the design flow. "Thermal is a big topic for everybody, and reliability is really what hits you if you don't consider thermal," he added.
Samta Bansal - EDA Work Must Start Early
Bansal talked about the work that Cadence has done over the past 5 years with customers and partners. She noted that 2.5D and 3D-IC designs are well underway, with interposer-based FPGAs, TSV memory cubes, logic and memory on interposer, and wide I/O logic-plus-memory chips coming into production over the next few years. "EDA has to start working 3 to 4 years before" production, she said.
To bring 3D-ICs into the mainstream, standards are essential, Bansal said. So are EDA tools. What must be understood, she said, is that 3D-ICs will be heterogeneous devices, including custom, digital, and package design. "This means a 3D solution has to extend across custom, digital, and package, and that's what we did," she said. "All these different tools have to understand the TSVs, the microbumps, the backside metal layers, and the associated rules and models." Cadence, she noted, has both a complete tool set for 3D-IC and several years of experience through test chips and production chips.
Dusan Petranovic - Getting Ready for Interposers
Petranovic (Mentor Graphics) noted that the recent interposer-based Xilinx FPGA has brought 2.5D ICs into focus, and in the short term, he said, "we have to upgrade and define the tools to design interposer based chips." But work on 3D-ICs must still go ahead because 2.5D implementations will not fit all applications. In the medium term, Petranovic said, 3D-IC design tools will be available for architectural exploration, thermal and stress-aware analysis and verification, physical verification, and interaction modeling.
In the long term, Petranovic expects to see monolithic 3D-ICs, a technology discussed in more detail by Sekar of Rambus. Heterogeneous integrations with MEMS, nano-electronics, and opto-electronics are also possible. Returning to the present, he discussed physical verification support for 2.5D and 3D-ICs.
Steve Smith - Not Yet Time for Standards
The 3D "ecosystem is happening," according to Smith (Synopsys), but it is much more complicated than previous ecosystems because we're dealing not only with EDA companies and foundries, but also packaging providers, materials manufacturers, and outsourced assembly and test (OSAT) suppliers. He noted that a lot of the original work on thermal and mechanical stress analysis was done with Synopsys TCAD (technology CAD) tools, and said signoff tools need to understand constructs such as TSVs and micro-bumps.
In a remark that drew some later controversy, Smith said that "I'm probably the only one on the panel who doesn't support the idea that we need standards today. I think we have to work on solutions first. Standards will naturally evolve, but they're not the number one priority in my opinion."
Deepak Sekar - A Monolithic 3D-IC Perspective
Sekar presented a 3D-IC technology unlike anything discussed so far at the EDP Symposium - the monolithic 3D. In conventional TSV technology, he explained, transistors are made on separate wafers at high temperature, and then the die is thinned and aligned and bonded to the bottom wafer. With the monolithic approach, you make the bottom wafer, transfer a thin layer of silicon, and build transistors on top of this. The key constraint is making transistors at less than 400o C.
"The key advantage to this approach is that the TSV sizes are closer to minimum feature sizes, so you have a real 3D-IC," he said. His presentation slide suggested that TSVs can use a pitch of 50-100 nanometers. However, he noted, "this type of technology needs a lot of EDA support. It's not as simple as regular TSV technology." For logic-on-logic stacking, he said, "you'll need a whole new set of EDA tools" that can handle TSVs close to the minimum feature size. His advice to EDA vendors: "make sure your algorithms are scalable to smaller TSV sizes."
Some Questions and Answers
Q: Everybody says thermal is a challenge. Are we doing something about it?
Bansal: There's a lot of work going on. From a tool perspective we are analyzing it. There is talk about having extra TSVs to let the heat out.
Sekar: Doing 3D itself reduces the power. If you can run a chip at a lower clock frequency and get the same performance, that helps reduce the power. Techniques where you design the power grid as a heat sink also help. People are trying to develop better thermal interfaces and better heat sinks.
Marcoux: I consult with Allvia, the first TSV foundry. A lot of people have speculated about the use of TSVs as thermal vias, but the work funded at Allvia has thus far been a mixed bag. That's why I threw out the concept of two sizes of vias [tungsten and copper]. Thermal and assembly issues are intertwined and until we get assembly issues under control, I'm not sure we'll have good thermal solutions.
Q: What kind of accuracy is needed for 3D-IC? Do we need 3D field solvers?
Petranovic: If you want to retroactively extract interactions of TSVs, you need field solver accuracy. The alternative would be to come up with some parameterized models, but they cannot account for all situations.
Smith: For the basic analysis of the stress and thermal interactions of TSVs, you need field solver accuracy. Typically there you're dealing with maybe 10 TSVs in a pattern, but I think that's enough to give you some knowledge on the direction of stress.
Bansal: I think it's a combination. You need the field solver solution at the signoff stage, but in earlier stages you can use RLC circuit models. Sometimes our customers find critical nets and run full simulation on those before jumping into the field solver methodology.
Q: The research community is talking about glass interposers. Any thoughts there?
Sekar: Glass could be cheaper, but there's not much adoption and the infrastructure isn't there yet.
Reiter: Glass is a thermal insulator. If a CPU is getting hot, a DRAM on the other side of the interposer could be running at less than 85 degrees. The economics are clearly coming into place, but the big problem is that drilling glass for TSVs is not that easy. They are using lasers, but you are shooting a lot of heat through the glass foil, and the glass looks really ugly.
Q: Where are we on the timeline for standards? Steve [Smith], why are you not interested in standards?
Smith: I've been in EDA for 30 years, and successful standards efforts come from de-facto use in volume. We have to get some work done first. Standards will come, but are not needed initially.
Bansal: We have to keep making progress. At the same time, standards discussions have to start. If we want 3D-ICs to become mainstream, the standards effort has to start now because it will take a couple of years to get there.
Reiter: At Sematech I see Intel and IBM sitting next to each other and agreeing on ways to do things. It's remarkable. As soon as people know which direction things are going, it's much easier to join the team. So it's important for the industry that somebody steps forward.
Previous Blog Posts from EDPS 2012
Industry Insights "EDA Symposium: Users Cite 3D-IC Design Tool Needs"
Industry Insights "EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs"
EDA360 Insider "Want a peak at a possible Qualcomm 3D IC roadmap?"
EDA360 Insider "3D preview from EDPS: Qualcomm's Director of Engineering Riko Radojcic talks 3D and 3D EDA"