Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Six months ago, I wrote about a lively panel discussion at PCB West about printed circuit board data transfer standards. Most panelists - and many audience members - were supportive of IPC-2581, an "intelligent" data format that can potentially replace the various formats that designers use today. It can only become a true industry standard with strong backing from the industry - and that's exactly what has been happening with the new IPC-2581 Consortium over the past six months.
Here's some quick background. The venerable Gerber format can transfer image data, but it can't transfer stackup data, materials information, design intent, or netlists. Therefore, PCB designers typically ship multiple files in multiple formats to fabrication and assembly houses. One attempt to create a more intelligent format was ODB++, but with the acquisition of Valor by Mentor Graphics in 2010, that format is now owned by Mentor. Thus, there's a renewed push behind IPC-2581, which was initially released in 2004, as a neutral, open industry standard.
Cadence led the effort to create the IPC-2581 Consortium, which was introduced at last year's panel. Its stated goal is "to accelerate the adoption of IPC-2581 as an open, neutrally maintained global standard to encourage innovation, improve efficiency and reduce costs." In addition to Cadence and Zuken on the EDA side, the consortium represents EMS companies, OEMs, and fabrication, assembly and test companies. 26 member companies are currently listed on the consortium web site.
Building a Consortium
To get an update on the consortium I talked to Gary Carter, who heads up the CAD engineering organization for the Network Communications Division of Fujitsu in Richardson, Texas. He chairs the OEM working group in the consortium. (There are two other working groups. The Technical working group is chaired by Ed Acheson of Cadence, and the Awareness/Promotion working group is chaired by Hemant Shah of Cadence, who also serves as leader of the overall consortium.)
The OEM working group includes Fujitsu, Harris, NVidia, Cisco, and Ericsson. "We're trying to get the OEMs to put the hard press on their supply chains to get adoption of the 2581 standard as quickly as we can," Carter said. Why is this important to Fujitsu and other OEMs? Because IPC-2581 will provide a non-proprietary standard for manufacturing and assembly data, Carter said. "We feel it is really important to have a neutral standard," he said. "The big thing is having a lot more data-driven intelligence, and the ability to move away from paper-based, human interpreted formats."
One accomplishment of the consortium, Carter said, is its membership roster. "Folks who are direct competitors have really gotten together and worked on an initiative with a common goal in mind," he said. "I see this as a big endorsement for getting this standard in play."
Another key accomplishment is validation, an activity driven by the Technical working group. Basically, the consortium has published a validation matrix showing that test case data produced by Cadence and Zuken has been correlated and validated against proprietary manufacturing formats by several independent companies, including Adiva, Easylogix, DownStream, and Wise Software Solutions. In its first phase, the validation flow includes artwork, NC drill data, and NC route data.
IPC-2581 Consortium validation flow
The goal of the matrices is to define and document the validation of IPC-2581 export against current exported data formats such as Gerber, ODB++, NC Drill, and others. At this point, Carter observed, the focus is on fabrication data and on ensuring that IPC-2581 can produce everything it takes to build a bare board. This has been proven to work, and the next level of validation is on the assembly side. "At that point, we should be able to do everything ODB++ can do and maybe a little more," he said.
Carter said his personal goal is to be able to complete a bare board pilot project and demonstrate it at the PCB West conference in September 2012. "My ‘stretch' is to try and get through assembly," he said.
Meanwhile, he noted, the consortium is working on the next revision of the IPC-2581 standard. One likely addition is support for back-drilling, which Carter said is particularly important for backplanes. Consortium members are also discussing support for technologies such as buried components and Flex circuits.
In addition to the validation matrix, validation viewers from Wise Software, DownStream, and Easylogix are available for downloading from the consortium web site. The consortium has also made three IPC-2581 designs available for viewing with any of these free viewers.
When Will It Be Ready?
So when will IPC-2581 be ready for mainstream adoption? Carter is looking for that to happen around the end of 2012, at least for "revision A" status. It's all about "getting this group of committed consortium members to stand up and say their validation is complete, and they've got a set of tools that people can use," Carter said.
Footnote: I posted a message about my PCB West 2011 blog to the LinkedIn PCB Designers group, and when I last looked it had 42 comments. One was from a Mentor Graphics representative who said that "certainly Mentor plans to support IPC2581 into its manufacturing tools; we are committed to following what our customers need." Conclusion: Things are looking good for IPC-2581 as a widely adopted industry standard.