Get email delivery of the Cadence blog featured here
It's that time of the year again! The 49th Design Automation Conference (DAC 2012) is just a little over one month away, and Cadence will have an active presence on the exhibit floor, on panel discussions, in tutorials and workshops, in the user track, and in a co-located event that includes a 10-year OpenAccess celebration.
A new Cadence DAC microsite has details, and shows how you can sign up for a free three-day exhibit pass through the "I Love DAC" program. Meanwhile, mark your calendar and reserve your ticket now for the world famous (in the EDA world, anyway) Denali Party by Cadence Tuesday evening June 5.
This year's DAC will be held June 3-7 at the Moscone Convention Center in San Francisco. The conference includes keynote speeches by executives from ARM, Intel, and IBM; 24 panels, including "pavilion panels" on the show floor; Monday tutorials; co-located conferences and events; a Chevy Volt teardown; a robust technical paper program; and over 200 exhibitors. For a general overview, see the DAC web site. Register by May 7 for the best rates.
Another important deadline is May 15. Until then, you can obtain a free three-day exhibit pass through the annual "I Love DAC" program co-sponsored by Cadence, Atrenta, and SpringSoft. Exhibits run Monday-Wednesday, June 4-6. "I Love DAC" attendees will have access to all keynote sessions and all four evening receptions. For details, see the DAC microsite.
On the Exhibit Floor
The Cadence booth is #1930, and it will feature a variety of live presentations that provide real-world solutions to IC and system design challenges. The ChipEstimate.com booth is #1202, and here you can learn about the latest in IC design and verification IP.
DAC Panel Discussions
Here are several panels with Cadence participation. For a complete list of DAC 2012 panels, click here.
System Models - Does One Size Fit All?Time: 1:30 PM - 3:00 PM, Tuesday June 5
Developing a single model that simultaneously satisfies the needs of software developers, system architects, hardware developers and verification engineers is hard. Is it possible for one size to fit all? Who will provide the models? Who will pay for them? The panelists will review different aspects of system modeling and discuss which abstraction levels best address specific user requirements.
Stuart Swan of Cadence will appear on panel with speakers from Qualcom, ARM, Research in Motion, and Tensilica. Brian Bailey of the EE Times EDA DesignLine will moderate.
High-Level Synthesis Production Deployment: Are We Ready?Time: 9:00 AM - 10:30 AM, Wednesday June 6
High-level synthesis has historically over-promised and under-delivered, but that is all about to change. Or, is it? Are we ready to climb the ladder up to the next level of design abstraction? Watch panelists debate whether today's technology can handle system validation, IP integration and optimization, power/performance constraints, and design verification challenges.
Mark Warren of Cadence will appear on a panel with speakers from Intel, NEC, Freescale, Xilinx, and Calypto Design Systems.
Is 3-D Ready for the Next Level?Time: 9:00 AM - 10:30 AM, Thursday, June 7
Early promises of 3D IC integration have now been realized in volume production. What have the design and supply chains learned from the experience of enabling these applications? What will be the next killer applications for 3-D, how will these be enabled across the semiconductor industry, and what key technologies must the EDA industry contribute?
A.J. Incorvaia of Cadence will appear on a panel with speakers from IBM, Intel, Xilinx and TSMC.
Cadence Speakers at Monday Tutorials
Tutorial 2: Enough Talk! Practical Approaches to 3D-IC - TSV/Silicon Interposer and Wide I/O Implementation From People Who Have Been There and Done ThatSpeaker: Marc GreenbergTime: 8:30 AM - 10:30 AM, repeated at 11:30 AM - 1:30 PM, and again at 3:30 PM to 5:30 PM
Tutorial 4: Understanding and Overcoming Patterning-Induced Design Challenges in the 20nm and 14nm Technology NodesSpeaker: Vassilios GerousisTime: 8:30 AM - 10:30 AM, repeated at 11:30 AM - 1:30 PM, and again at 3:30 PM - 5:30 PM
Tutorial 5: Analog and Mixed-Signal Design at Advanced Process NodesSpeakers: Jim McMahon, Stacy Whiteman, Fang-Cheng Chang Time: 8:30 AM - 10:30 AM, repeated at 11:30 AM - 1:30 PM, and again at 3:30 PM - 5:30 PM
DAC Workshop - "More than Moore"
DAC Workshop on More than Moore Technologies8:30 AM - 6:00 PM, Sunday, June 3
This workshop focuses on "More than Moore" technologies that will make it possible to reach 10nm and below. Leading experts from industry and academia will offer presentations in three areas of focus - 3D integration, novel memories, and on-chip optics. These presentations will be followed by a panel discussion titled "Are Models and Design Flows Ready for More than Moore?" Samta Bansal of Cadence will participate in the panel, along with speakers from eda2asic, Qualcomm, IBM, Mentor, and Intel.
Co-Located Conference - Si2 Standards and OpenAccess Celebration
Si2 Round-Up @ DAC: Standards in Action9:00 AM - 6:00 PM, Monday June 4
This day-long conference has four sessions and includes several Cadence presenters. Sessions include the Open Process Specification (OPS), DRC+, an OpenAccess 10 year celebration, and standards for a 3D world. An open luncheon is part of the OpenAccess 10 year celebration. (For background, see my recent blog post).
The Denali Party by Cadence
The Denali Party by Cadence will be held Tuesday June 5 from 8:30 pm- 12:30 am at the Ruby Skye nightclub, just off Union Square in San Francisco. The party will include the EDA's Got Talent competition, which will be expanded this year to all forms of talent, not just singing. Reserve your ticket now. Space is limited!
See you at DAC 2012!