Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
In late April, a wealth of information on IC functional verification became available at the DVCon web site. Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can view the list of sessions here.
Cadence contributed heavily to DVCon this year, and what follows is a listing of Cadence-authored or co-authored papers now available for viewing and downloading. Happy reading!
Session 1: Low Power TechniquesPaper: The Case for Low-Power Simulation-to-Implementation Equivalence CheckingPresented by: Himanshu Bhatt, Cadence
Summary: I attended this paper, and found it to be a good summary that shows how equivalence checking fits into the low-power verification flow. While power formats unify intent, the paper notes, implementation and verification tools may interpret the information differently. Equivalence checking can formally prove that simulation matches the original power intent and RTL.
Session 1P: Poster Session 1Paper: PSL/SVA Assertions in SPICEPresented by: Donald O'Riordan, Cadence
Summary: This paper shows how Property Specification Language (PSL) and SystemVerilog Assertions (SVA) assertion semantics can be extended to, and evaluated within, a SPICE-based simulator. It presents multiple examples and simulation results.
Paper: New Challenges in Verification of Mixed-Signal IP and SoC DesignPresented by: Qi Wang, Cadence
Summary: Mixed-signal blocks with advanced power management techniques can pass simulation but fail in silicon. This paper proposes that a static verification methodology can help catch electrical failures.
Session 2: UVM TechniquesPaper: Register This! Experiences Applying UVM RegistersPresented by: Kathleen Meade, Cadence
Summary: Controlling and monitoring registers and memories comprises a large part of typical functional verification projects. This paper shows how the Accellera UVM-REG register and memory package can help, and provides some practical guidelines for register management gleaned from real project experience.
Session 2P: Poster Session 2Paper: UVM Do's and Don'ts for Effective VerificationPresented by: Kathleen Meade, Cadence
Summary: This presentation provides tips and best practices using specific pointers and code examples, gathered from live projects worldwide. Topics include configuration, the objection mechanism, the register package, and transaction level modeling (TLM).
Session 4: Verification Benchmarking and EfficiencyPaper: Yikes! Why is My SystemVerilog Testbench so Slow?Presented by: Justin Sprague, Cadence
Summary: While SystemVerilog added many useful new features, many verification engineers have experienced slower simulation. This paper shows why - and tells what you can do about it.
Session 6: Mixed-Signal VerificationPaper: From Spec to Verification Closure: A Case Study of Applying UVM-MS for First Pass Success to a Complex Mixed-Signal SoC DesignPresented by: Neyaz Khan, Maxim
Summary: This paper shows why metric-driven verification and UVM are needed for mixed-signal verification, and presents an example based on a noise cancelling receiver block within a mixed-signal SoC. I attended and wrote a blog post about this paper.
Session 7: Verification and Debugging TipsPaper: Memory Debugging of Virtual Prototypes with TLM 2.0Presented by: George Frazier, Cadence
Summary: Memories are commonly modeled as TLM 2.0 components in SystemC-based virtual prototypes. This paper shows how TLM 2.0 memory debugging can be used to investigate problems familiar to virtual prototype designers.
Session 8: Getting to Coverage ClosurePaper: Bringing Continuous Domain into SystemVerilog CovergroupsPresented by: Prabal Bhattacharya, Cadence
Summary: This paper proposes a set of requirements for specifying functional coverage in an analog or mixed-signal block. It explains how the real number data type can be introduced into a SystemVerilog coverpoint specification, enabling a complete coverage specification for a mixed-signal verification environment.
Note: An audio archive of the DVCon 2012 panel, "The Resurgence of Chip Design," is available here. You can listen to individual sections of the panel or download the full MP3 file. My blog summary of the panel is located here.