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This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
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Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
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Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49th DAC in San Francisco.
Tuesday June 5
Addressing Hardware/Software Co-Development, System Integration, and Time to MarketTime: 8:00 AM - 10:00 AM (doors open and breakfast is served at 7:30 AM)Location: 270-276 (Moscone Convention Center)
This breakfast will feature speakers from Cadence and LSI Corp. Speakers will present the following topics:
The breakfast session will conclude with a panel discussion in which Cadence technologists and guests will answer your questions about system-level development challenges.
Wednesday June 6
The Path to Yielding at 2(x)nm and BeyondTime: 8:00 AM - 9:00 AM (doors open and breakfast is served at 7:30 AM)Location: 270-276 (Moscone Convention Center)
This breakfast will include speakers from Cadence, IBM and Samsung. A panel will look at process and design challenges at advanced nodes and discuss what it takes to ramp up to volume production. The panel will examine challenges from the foundry, EDA and customer perspectives.
Interested? Learn more about Cadence DAC lunches and breakfasts here
Register for lunches and breakfasts here
Learn about all Cadence DAC activities, including the Denali Party, here
See you in San Francisco!