Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Non-Volatile Memory Express (NVM Express or NVMe) is an emerging protocol standard for accessing solid state drives (SSDs) over PCI Express (PCIe) links. It would thus make sense, if you're designing an SoC that has an SSD interface, to cobble together a subsystem that includes an NVMe controller, PCIe controller, and PCIe PHY. But what if you could just buy a configurable subsystem that includes all of these components running under a common firmware layer?
You can, with the introduction this week (May 15, 2012) of the Cadence Design IP for NVM Express subsystem. The high level of integration makes it easy to drop the solution into an SoC, and opens some opportunities for optimization that would otherwise be difficult.
So why NVMe? In many designs, the system bottleneck has moved from computing to data access. Reducing latency and boosting throughput are becoming critical requirements. PCIe-based storage solutions for NAND flash are thus making inroads, but many such solutions have used non-standard protocols. Existing standards such as Fibre Channel and Serial ATA (SATA) were not created with SSDs, virtualization, and high I/O operations/second in mind.
The NVM Express specification was released in March 2011 by the NVMe Work Group, whose web site is a good source of information about the standard. NVM Express 1.0 defines an optimized register interface, command set, and feature set for PCI Express SSDs. In addition to leveraging high-performance PCIe as its transport layer, NVMe is scalable from low-end client devices to high-performance enterprise applications. It supports up to 64K outstanding requests, offers end to end data protection, and robust error reporting.
A Configurable Subsystem
The Cadence announcement provides a complete PCIe and NVMe solution. "What we're delivering is not just an NVMe controller," said John Tam, product marketing director for SoC Realization at Cadence. "It's a complete subsystem that integrates multiple pieces of IP with firmware, and with verification environments, to make it much easier for people to put NVMe into their designs."
The diagram below shows how an NVMe subsystem (at lower left) might fit into an SSD controller SoC. The subsystem includes a PCIe PHY, PCIe controller, NVMe controller, and an extensible firmware API. It also comes with NVMe verification IP, which was announced separately in March 2012. One advantage of the subsystem approach, Tam noted, is that SoC integration is much easier compared to assembling the various components manually and making sure they all work together.
Another perhaps less obvious advantage is the optimization that becomes possible through the subsystem approach. For example, Cadence has been able to optimize the subsystem in the following ways:
The bottom line? "By looking at this subsystem as a whole, we can reduce the latency, improve the throughput, and reduce the CPU overhead," Tam said.
The Cadence Design IP for NVM Express subsystem is important not only because it will ease the adoption of NVMe. It also represents a direction that IP providers will need to take in order to address the levels of SoC complexity that will very quickly be upon us.