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Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference (DAC 2012) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday, June 4, and from 9:00 am to 5:00 pm Tuesday and Wednesday, June 5 and 6. There is also a Cadence demo at the ARM Pavilion, as noted at the end of this post.
A complete demo suite schedule is available here. Below, to better help you find demos of interest, I've grouped them according to 12 general categories. These categories also happen to be hot topics in today's EDA industry.
To register for demos, click here.
1. Package/Board Aware IP
Monday 10 am, Tuesday 10 am -- Optimizing Packaged ICs for System-Level Electrical Compliance using Package-Board-Aware IP
Tuesday 5 pm, Wednesday 10 am -- Exploring 3D-IC using IC Package-Driven Silicon Interposer Technology
Monday 10 am, Tuesday 12 noon, Wednesday 9 am -- Realizing 3D-IC Design using an Integrated IC Design Solution
3. HW/SW Integration and Co-Development
Monday 11 am, Tuesday 1 pm, Tuesday 4 pm, Wednesday 2 pm -- Virtual Prototyping for Early Software Development and System Validation using the Cadence System Development Suite
Monday 2 pm, Monday 5 pm, Tuesday 11 am, Wednesday 12 noon -- System Development Suite: HW/SW Integration and Early Software Development using the Cadence Rapid Prototyping Platform
4. Verification IP (VIP)
Monday 4 pm, Wednesday 11 am -- Accelerating SoC Development, Verification, and HW/SW Validation using the Cadence Verification IP Catalog (Featuring Accelerated Verification IP)
Monday 12 noon, Tuesday 2 pm -- Shortening IP Integration and Verification Time for SoC Development with Third-Generation Protocol Compliance using the Cadence Verification IP Catalog
Wednesday 3 pm, Tuesday 5 pm -- Verifying Advanced Memory Interfaces and Addressing System Integration within Your Existing SoC Environment using the Cadence Verification IP Catalog (Featuring Memory Models)
5. Functional Verification
Monday 2 pm, Tuesday 1 pm, Wednesday 11 am -- To UVM and Beyond! UVM-Based Advanced Verification Topics
Monday 3 pm, Tuesday 12 noon, Wednesday 1 pm, Wednesday 5 pm -- Extending Metric-Driven Verification to TLM and Leveraging High-Level Synthesis for Multi-Level Verification and Faster Hardware Design and IP Development
Monday 1 pm, Tuesday 3 pm, Wednesday 4 pm -- Leveraging the Best of Acceleration and Emulation for Rapid SoC Development and Verification
Monday 1 pm, Tuesday 12 noon, Wednesday 10 am -- Improving Debug Productivity using the New Incisive Debug Analyzer for e and SystemVerilog Testbench Verification
Wednesday 10 am -- Increasing Productivity using a Comprehensive Formal Verification Solution: Encounter Conformal Technology
6. Custom/Analog Design
Monday 9 am, Tuesday 5 pm, Wednesday 1 pm --- Addressing Throughput and Usability During the Characterization of Standard Cells, Complex I/O, and Memories
Monday 10 am, Tuesday 3 pm, Wednesday 12 noon -- Detecting and Fixing Layout-Dependent Effects using Virtuoso Technology
7. Mixed-Signal Design and Verification
Monday 9 am, Wednesday 2 pm -- Boosting Productivity and Reducing Turnaround Time with an Integrated Mixed-Signal Physical Implementation Flow
Monday 12 noon, Tuesday 2 pm -- Addressing Mixed-Signal Functional Verification Challenges using Virtuoso Multi-Mode Simulation
Monday 3 pm, Wednesday 4 pm -- Improving Verification Coverage and Reducing Silicon Re-Spins for Functional and Low-Power Verification of Mixed-Signal Designs
8. Low Power Design
Monday 5 pm, Tuesday 10 am, Wednesday 3 pm -- Optimizing Power, Reducing Energy, and Meeting Schedule using an Advanced Low-Power Solution
Monday 9 am, Tuesday 1 pm -- Meeting Power Targets using a Digital Front-End Design and Verification Solution
9. 28nm/20nm and Beyond
Monday 11 am, Tuesday 4 pm, Wednesday 4 pm -- Managing Double Patterning Complexity within the Virtuoso Environment
Monday 1 pm, Wednesday 5 pm -- Realizing the Power, Performance, and Area Potential of 28/20nm Design using Encounter Digital Implementation System
Monday 2 pm, Tuesday 4 pm -- Accelerating Giga-Scale Design Schedules using Encounter Digital Implementation System
10. ECO Automation
Monday 4 pm, Tuesday 11 am, Wednesday 5 pm -- Maximizing ECO Automation and Improving Turnaround Time using Functional and Multi-Mode, Multi-Corner (MMMC) Signoff-Driven ECO Flow
11. Advanced Signoff Analysis
Monday 5 pm, Tuesday 9 am, Wednesday 3 pm -- Meeting Yield and Quality Requirements with Advanced Physical Design Signoff: Custom and Digital DFM and Physical Verification
Monday 3 pm, Tuesday 10 am, Wednesday 1 pm -- Achieving Faster Timing and Power Closure using an Advanced Digital Signoff Analysis Solution
Monday 4 pm, Tuesday 11 am, Wednesday 2 pm -- Achieving Faster Turnaround Time and Predictable Convergence using an Extracted View-Driven Electrical Signoff Flow
12. Integrating ARM Cores
Monday 11 am, Tuesday 2 pm, Wednesday 11 am -- Implementing Low-Power and High-Performance ARM® CortexTM Processor-Based SoCs (2 part, 2 hour presentation)
An overall view of Cadence activities at DAC 2012, including conference speakers, breakfasts, lunches, and the Denali Party, is available here.
ARM Pavilion Demo -- System-to-Silicon Solution for big.LITTLE Processor Based SoCs
In addition to the demos listed above at the Cadence booth, Cadence is offering a demo at the ARM Connected Community Pavilion (booth 802) at the Cadence "big.LITTLE System-to-Silicon" pod. The demo summarizes the System Development Suite and implementation capabilities for big.LITTLE, and highlights NIC-400 interconnect performance analysis and verification. It includes coherent fabric verification and architectural exploration. Times are:
Monday: Noon, 3 pm, and 4 pmTuesday: 9-Noon and 3 pmWednesday: 9-11 am and 3 pm
Why this demo? Multi-core heterogeneous SoCs have complex traffic interactions that impact overall system performance. Verification of these complex interconnects, with cascaded sub-system fabrics, is difficult, especially while making rapid changes to tune performance. The demo will show an automated solution for performance analysis and verification automation.