Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
In the early 2000s we hit a power "wall" and decided to scale it by putting multiple processor cores on a single chip. But the multi-core era is running into limitations, and it's time to start planning for a "new era" in which design innovation will fuel performance growth, according to Design Automation Conference (DAC 2012) keynote speaker Joshua Friedrich (right), senior manager of POWER technology development in IBM's Server and Technology Group.
Friedrich gave the first part of a two-speaker keynote titled "Designing High Performance Systems-on-Chip" June 6. Brad Heaney, Intel Architecture group product manager, gave the second part, which showed how Intel developed the 3rd Generation Intel Core Processor (code named Ivy Bridge). Both speeches are available in a video recording at the DAC web site. This blog post focuses on Friedrich's talk.
While multi-core architectures are providing tremendous benefits, it's important to realize that multi-core performance growth will face limitations in the near future, Friedrich said. "This will require designers to innovate more rather than just include more cores in a design in order to make effective use of the transistors Moore's Law will give us," he said. He spoke of three areas that need innovation now - the hardware/software boundary, heterogeneous IP for processor subsystems, and emerging system-level technologies.
The Good Old Days
Friedrich started his talk with a look at the "good old days" of Denard scaling, which provided exponential single-threaded performance growth into the mid-2000s. All transistor dimensions went down by a predictable factor at each node, operating voltage went down, and frequency went up. During this time IBM went from the 1 GHz POWER4 processor to the 5 GHz POWER6 (produced in 65nm SOI technology).
But "physics brought this era of single-threaded performance to a close," Friedrich said. "Somewhere around the 90nm node we were no longer able to keep scaling the oxide thickness, and therefore couldn't drop the voltage further. Passive power was on pace to exceed active power. Something had to change and it did - frequency stepped back, and single-threaded performance growth slowed greatly."
Since there was no longer much value in merely shrinking dimensions of transistors, new innovations such as low-k interconnects, high-k metal gates, eDRAM, and strained silicon appeared. But the shift was underway, Friedrich said, from single-threaded performance and frequency to a new focus on multi-core design and throughput. IBM in fact led the charge with the dual-core POWER4, which was introduced in 2001. More recently, the POWER7 achieved a 5X increase in throughput per socket by increasing cores from 2 to 8, with only slightly improved thread performance.
Limitations of Multi-core
In spite of multi-core advancements, Friedrich said that "some fundamental limiters are beginning to surface that indicate that the growth we can expect to achieve from multi-core will begin to slow in the future." These include:
Friedrich didn't directly mention the difficulty of programming multi-core devices, which many people see as the biggest obstacle.
So what's needed to get the best use out silicon? "We believe the answer lies in a new era of system-focused performance growth driven by designer innovation rather than simply by technology," Friedrich said. He identified three key areas of focus as listed below.
Friedrich had much to say about how EDA tools can help. One way is to help designers manage complexity, especially with new technologies like double patterning or 3D packaging. Another is to leverage statistical timing rather than relying on multiple fixed-corner timing runs. Friedrich also called for leveraging sequential synthesis techniques like retiming.
Processor design, Friedrich said, needs a methodology that "combines the best elements of an ASIC style design approach alongside the traditional elements of processor design." Such an approach is already underway at IBM, which is shifting away from hand-placed, hand-routed designs to "more of a synthesis based approach," he said. IBM has been able to limit the number of custom blocks and to reduce the number of partitions. "In our most recent design we reduced the number of blocks by about 30% and we plan to achieve a 5-10X reduction over the next two generations in the number of hierarchical partitions," he said.
"We need EDA tools to provide more productivity to enable designer innovation, so our focus can shift away from technology and implementation and towards creating features and functions," Friedrich concluded.
Industry Insights blog posts about DAC 2012
ARM CTO at DAC 2012: The Truth About Semiconductor Scaling
DAC 2012 Panel - Can One System Model Serve Everybody?
DAC 2012: EDA Industry Celebrates 10 Years of OpenAccess
TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem
Gary Smith at DAC 2012: Multi-Platform Design and the $40M System on Chip
This is a good overview of the upcoming challenges. Still, this analysis is may be too HW centric. There is a whole lot of innovations that can be unleash if we could finally reconcile the SW architects and the HW architects even using current technologies