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Analog design is almost entirely a manual effort, and that needs to change, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, Daglio shows how analog/mixed-signal constraint capture and propagation can be automated, and how STMicroelectronics is working with Cadence to make that possible.
The presentation, titled "Analog Design Intent Capturing," was one of 30-plus customer and partner presentations at the EDA360 Theater in the Cadence booth at the Design Automation Conference (DAC 2012). Audio recordings and slides from most of the presentations are located here, and a previous blog post lists the titles of the available presentations.
Two years ago, Daglio noted, STMicroelectronics began looking at the design effort for analog/mixed-signal IP blocks. It turned out that much of the effort was in layout, because there was very little automation there. "Analog design is suffering from a lack of formalism and automation," he said in the presentation.
The digital world, Daglio noted, has technologies such as RTL synthesis, timing-driven placement and routing, formal verification, static timing analysis, and metric-driven verification. Digital designers use formats and standards like CPF, UPF, Verilog, Liberty, LEF/DEF, and more. "In analog, you are basically stuck with a SPICE netlist," Daglio said. "Automation is very poor and everything is at a netlist level."
What STMicroelectronics is trying to build, Daglio said, is a "real and consistent analog design flow" based on a standard taxonomy, data exchange formats, abstracted views, data reuse, interoperability, and standardization. Such a flow has been available for digital designers for the past 10 years, he noted, so why not analog?
Daglio described a flow in which analog design intent is captured from the schematic and propagated down to layout tools. At the same time, layout tools can back-annotate physical constraints to the schematic. Constraints can be mapped between electrical and physical domains.
STMicroelectronics has been working with Cadence on several prototypes that use the Virtuoso Circuit Prospector to extract intent information from the schematic, and the Virtuoso Constraint Manager to pass constraints among the various tools in the flow. For example, Daglio talked about the ability to automatically detect a circuit mirror or differential pair on the schematic, generate electrical and physical constraints, and propagate the constraints to layout tools.
He noted that STMicroelectronics and Cadence have developed four prototypes. The very first one demonstrated a link between Circuit Prospector and Constraint Manager. More recently, the companies have been able to demonstrate the automatic generation of constraints in ADE-XL and Constraint Manager. The main gap now, Daglio said, is the ability to export constraints in a standard language to third-party tools - and he cited ongoing work with Cadence to generate constraints in a format that can be exported.
Standardizing and formalizing analog design intent, Daglio said, would enable correct-by-construction designs, allow fast re-implementation of analog/mixed-signal IP, and boost novice designer productivity. "We are closing the gap to have an optimized flow for analog/mixed-signal IP," he concluded.
You can listen to the 25-minute presentation here.