Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Martin Lund joined Cadence in early 2012 as senior vice president of R&D for the SoC Realization Group. He hasn't worked for an EDA company in the past, but 12 years at Broadcom -- most recently as senior vice president and general manager of Broadcom's Network Switching Business -- gave him a hands-on perspective on the challenges of system-on-chip (SoC) design and IP integration. Today he's responsible for the growing portfolio of design IP and verification IP at Cadence.
In this interview Lund talks about his background, the charter of the SoC Realization Group, the challenges of SoC design and IP integration, IP quality, the emergence of the "IP Factory," and trends in verification IP.
Q: Martin, where were you before joining Cadence this year?
A: At Broadcom, I was general manager of the Network Switching Business unit for 9 years. The division handles everything involving packet switching, from the smallest switches that you would buy for your home office all the way up to the stuff that runs Google and Amazon data centers. We were in the largest routers in the world.
Before Broadcom I was at Intel. I was part of an acquisition that Intel did in 1996 of a European networking company called Case Technology. They made routers and switches.
Q: Were you involved with EDA tools or commercial IP at Broadcom?
A: We were heavy users of both. We used a lot of EDA tools and we were a large emulation user. We used third-party IP once in a while, and most of the time it turned out to be more painful than it was worth, because the quality was not what we would want.
Q: Coming to Cadence must be quite a change! What brought you into the world of EDA and IP?
A: I've known Lip-Bu Tan [Cadence CEO] for years. I think you have to live to learn, and after 12 years at Broadcom it was a good time to go and do something new.
I started as a systems guy and did that for a decade. Then I did semiconductors for a little over a decade. Going into another area that has a broad industry impact was very appealing to me. I think there's an industry challenge to make IP as good as, or even better, than what the traditional semiconductor companies can do.
Q: How will your end user experience help you in your new role at Cadence?
A: After managing an organization at Broadcom for many years, I understand productivity and engineering dynamics and schedules. I understand that at the end of the day, our customers are building semiconductors that they have to sell with high quality.
Q: What is the charter and strategy of the Cadence SoC Realization Group?
A: We want to deliver high quality design and verification IP that can help our customers from a productivity perspective. We are building IP for new protocols and new process technologies, and we are helping the industry do work that we know is very hard.
Our strategy is to provide advanced IP that's relevant to our customers. We provide advanced protocols at leading-edge nodes, with a strong focus on tight integration of the complex analog and digital components that are needed for high-speed interfaces.
With verification IP [VIP], Cadence is the leader in terms of size, scope and scale. We provide proven VIP and memory models that enable people to get to market faster and with higher quality by making it easier to use the most advanced verification technologies for the newest protocols - whether they choose to acquire design IP or develop it on their own.
Q: What challenges and trends do you see today in SoC design and IP integration?
A: I think the biggest challenge is ever-increasing complexity. The challenge is to find ways to abstract or work with enough leverage that you can get to market fast enough, with a reasonable number of people on your team. People today are spending a tremendous amount of time on just putting basic stuff together and not enough time on differentiation. That's where design IP comes in.
When you have maybe 50 IP blocks, integration is a huge challenge. People are finding ways to group blocks together and are calling them "subsystems." Some people think about a subsystem as a complete vertical solution, but there's another way to think about it, which is the aggregation of multiple IP blocks. In fact a lot of designers inside semiconductor companies are building their own subsystems as means to manage the design and verification complexities.
Adding to this is the enormous cost and complexity of mixed signal designs at advanced nodes. As we get to 20nm and beyond it is becoming cost prohibitive for internal design groups to design physical IP to the desired quality level.
In addition, the end users of our technology have changed dramatically from being primarily other technologists to literally every consumer in every location around the globe. This new consumer base has higher quality expectations, and it demands the latest technology in a very short time frame, which is driving the rapid introduction of new protocol standards . The connection between the IP and VIP we provide and the demands of the end user is closer than ever before, which puts us in a unique position to be able to help our customers to meet the changing demands of their customers.
Q: You mentioned IP quality problems, and that's something people have been talking about for a long time. What needs to happen to improve IP quality?
A: There needs to be fanatical commitment to delivering quality. In the past, third-party IP has been very much a mom and pop shop type of approach, and having a hard commitment to quality is difficult in that scenario. I think that if you build chips that ship in the millions or tens of millions, and you understand the impact of being late or having to respin chips because of bugs that were found, that sets a different level of commitment to quality.
What we're doing at Cadence is taking a systematic approach. We're working to build a "factory" that will deliver repeatable, predictable quality. Predictability is huge. Applying our legacy of great, proven verification IP and advanced verification technologies will also give us a big leg up towards delivering quantifiably better quality design IP.
Q: You've spoken in the past about three phases of the commercial IP business - the Bazaar, the Superstore, and the Factory. Can you clarify those?
A: The majority of the industry is in the Bazaar. What people care about there is availability and price. If it's cheaper for me to buy this IP from you, I can save time to market, and you have it, great! The Superstore has another level of quality. If something doesn't work you can take it back. There's more of a selection and maybe you can get stuff put together if you ask nicely, but it's still about discrete commodities that sit on the shelf.
With the Factory approach, we're building a machine that can generate IP. That's a little bit like a fab. There is repeatability and predictability. What comes out at the end is not just a core that meets a given spec - it also comes with integration packaging information, signal integrity, thermal considerations and constraints, and software that allows you to plug it in and use it in a system very quickly. You can put building blocks together like Lego blocks and create your subsystem.
Q: How important is customization in commercial IP?
A: Everybody wants reusable cores. Reusability is a fantastic thing, but I think is somewhat of a fallacy. No two SoCs are the same. Everybody needs to customize their IP. With our IP Factory approach, we're taking that into consideration. We have built a machine that can deliver the IP that you need for your design, and still deliver predictable high quality. If you're building a network processor, the IP you need is different from somebody who is building a cell phone.
Q: What trends are you seeing in VIP?
A: Having VIP that is proven is critically important - the wider the variety of use cases verification IP has been exposed to, the higher the likelihood that it will find your bugs, too. At the SoC level, it's very important to have a comprehensive product portfolio encompassing not just the interface protocols, but all of the newest memory standards (like LPDDR3, SDCard 4.0, DDR4). And, you have to be in front of the leading edge, introducing the verification IP when, or often times even before, new standards are ratified. Advanced semiconductor companies need VIP very, very early, so when they're developing IP for a new protocol they have something to verify it against.
We are seeing a tangible shift to UVM (Universal Verification Methodology), and are proud to have built in the best support for this industry standard into our VIP for over a decade. In addition, as new verification technology is embraced -- like formal verification to support block level analysis and hardware acceleration -- having VIP to support these advanced verification techniques is critically important.
Q: If you look ahead 2 or 3 years, where do you see the IP industry going, and what does it mean for Cadence?
A: I think we're at the tipping point of significant acceleration of the use of high-quality, third-party IP. I think Cadence is uniquely positioned to participate in that marketplace. In fact, customers are constantly asking us to show up with high-quality IP. With the migration to more advanced process nodes the sheer amount of effort that it takes to build IP makes it very, very challenging to build everything in house. And if there's very little differentiation extracted from it, people are going to say, "why are we building it? We don't have to, why should we?"