Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows how his company implemented a metric-driven mixed-signal verification flow, and he discusses its advantages and challenges.
The presentation, titled "A Metric-Driven Verification Approach for Analog/Mixed Signal IP," was one of 30-plus customer and partner presentations at the EDA360 Theater in the Cadence booth at the Design Automation Conference (DAC 2012). Audio recordings and slides from most of the presentations are located here. Daglio also gave an EDA360 Theater presentation on analog intent capture, summarized here.
A metric-driven verification flow is a closed-loop approach (right) that creates an executable verification plan, collects and analyzes coverage metrics, measures progress, and automates verification tasks. It's been highly successful in the digital world. But why apply it to analog/mixed-signal IP verification? "It is almost impossible to have acceptable coverage closure with traditional verification approaches based on mixed-signal co-simulation," Daglio said.
He identified these advantages of metric-driven, mixed-signal simulation:
But there are challenges too. Daglio noted that metric-driven mixed-signal verification requires an additional, initial effort when it comes to defining good metrics for analog verification, creating a detailed verification plan, leveraging real-value models, specifying the hierarchy of transactions, and finding the right sampling rate and sampling windows. Perhaps most importantly, he said, "we need to create a new professional role - a mixed-signal designer who knows all the hard things about analog design, but who understands the advantages of using assertions, language, checkers, and coverage."
Experience at STMicroelectronics
Daglio noted that STMicroelectronics set up a previous mixed-signal verification environment using the Cadence Specman verification environment, a Fast SPICE simulator, and a digital simulation engine. It worked, but it was a multi-vendor environment, giving rise to communications problems between different tools. Long simulation runs were limiting verification closure. So STMicroelectronics decided to put together an all-Cadence verification environment.
This environment is based on the Cadence Incisive platform and uses Specman and the Virtuoso AMS Designer. It uses the Incisive Enterprise Manager for verification planning and Incisive Enterprise Simulator (referred to as NSim in the presentation) for digital simulation. The Specman "e" language environment generates stimulus for the circuit and measures the outputs. "Everything is managed by Specman," Daglio said.
While analog/mixed-signal models can be developed at several levels - including SPICE, Verilog-AMS, and VHDL-AMS - STMicroelectronics places a strong emphasis on Verilog-AMS wreal models, which can model continuous quantities in a pure digital simulator. Thus, wreal models are much faster than co-simulation using a Fast SPICE simulator. In the presentation, Daglio shows how Cadence has expanded the wreal data type beyond the Verilog-AMS language definition, and he also briefly compares wreal to real number modeling in other languages.
Daglio also showed how Specman can represent analog stimulus and trigger transistor-level analog events. He discussed mixed-signal assertions using Property Specification Language (PSL), and talked about how the Universal Verification Methodology (UVM) can be extended to bring metric-driven verification to mixed-signal environments. In future flows, he's looking forward to automatic generation and validation capabilities for analog behavioral models including wreal models.
Making it Work
The presentation closed with an example showing how the metric-driven environment works on a 130nm mixed-signal IP block. (This same example was presented in a "best paper" at CDNLive! EMEA in May. Cadence Community members can read it here). One interesting point is the number of languages and formats used - SPICE netlists, Verilog-AMS modules, UVM monitors, Verilog structural netlists, VHDL-AMS blocks, Specman "e," and PSL and SystemVerilog assertions with wreal datatypes. Everything is controlled from the Cadence irun environment.
The environment "is still a little complex," Daglio said, but there's some real automation that comes from Specman and from PSL assertions. He noted that Incisive Enterprise Manager allows automatic process, temperature and voltage variations, easing multi-corner verification. What's critical now, he said, is for companies to "grow the competency" to deploy metric-driven, mixed-signal environments.
The recorded audio presentation with slides is located here.