Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Real number modeling (RNM) provides a fast way to run a chip-level simulation with analog values, but support for it in the current SystemVerilog Language Reference Manual (2009 LRM) is very limited. A recently archived webinar shows how the next SystemVerilog LRM (which may be dated 2012 or 2013) offers new features that support RNM. It also shows how to write Verilog-AMS real-number models today that can be reused later in SystemVerilog.
Titled "Is SystemVerilog the Future of Mixed-Signal Modeling," the webinar was given by Dan Romaine, mixed-signal solutions engineer at Cadence. In the webinar, Romaine reviewed behavioral modeling choices, discussed the benefits of RNM, described support for RNM in various languages, presented additions to SystemVerilog 2012/2013 that will provide strong support for RNM, and showed how to write Verilog-AMS models for compatibility with SystemVerilog.
Romaine cited the growing amount of analog circuitry on today's SoCs, and noted that isolated analog and digital verification is no longer enough to reach tapeout. What's also needed is a chip-level functional verification that looks at the functional interactions between analog and digital blocks. But how to do it, given that a SPICE/RTL co-simulation would be much too slow?
One answer, Romaine argued, is real number modeling. This is a signal-flow based approach that uses real (floating-point, continuous) values to represent current or voltage in discrete time. It runs in a digital simulation environment and removes the need to use a much slower analog solver. In addition to allowing digital simulation speeds, RNM lets designers use digital verification techniques such as assertions, coverage, and metric-driven verification.
Romaine showed an example that compared transistor-level and RNM simulation times for a 14-bit ADC and DAC, which required 16,384 steps (2**14) for simulation. Transistor-level simulation took several days. RNM simulation took 3 seconds. This is an internal example from Cadence; Romaine also cited RNM testimonials from several customers.
RNM performance case study
Romaine then discussed the pros and cons of various modeling languages, focusing on their RNM support. Verilog, for instance, has very limited RNM support; you can use real variables inside a model, but there are no real variable ports. VHDL, on the other hand, supports real number ports, has custom/compound signals and ports that make it possible to pass both current and voltage, and offers custom resolution functions. The catch, of course, is that Verilog is far more widely used for digital design than VHDL.
Verilog-AMS is widely used for RNM. It supports real number ports and variables, along with 6 resolution functions on wreal nets. It has an analog solver if you need the accuracy, along with a discrete solver that can be used for real value equations. Cadence has developed and proposed some extensions to the Verilog-AMS wreal data type.
SystemVerilog, meanwhile, is making strong inroads into digital design and verification. Far more than just another version of Verilog, it also includes extensive verification features and an assertion language. But the 2009 LRM does very little for analog modeling. The upcoming 2012-2013 LRM, Romaine said, does far more. He previewed these features:
Romaine said these changes will appear in the next SystemVerilog LRM, which may be titled 2012 or 2013 based on when it's officially ratified. Cadence will implement these features, he noted. Romaine showed the following chart, which offers a good summary of the modeling features offered by various languages:
Modeling feature chart
If You Can't Wait
But what if you want to do some real-number modeling today? "What we're finding is that many customers who want to use the new SystemVerilog syntax are not willing to wait for it to be released," Romaine said. Therefore, Cadence has created a reusable way to write Verilog-AMS models that can be ported to SystemVerilog in the future. The trick is to avoid domains and disciplines, which exist in Verilog-AMS but not in SystemVerilog.
Therefore, Cadence has created six new "discipline less" wreal nets that combine resolution functions with data types - for example, wrealmin, wrealsum, and wrealavg. Romaine provided a code example showing how this is done. Once the new SystemVerilog LRM is implemented, these portable Verilog-AMS models can become SystemVerilog models. You'll just need to rename the file extension, and import a SystemVerilog wreal type package, which will be provided by Cadence.
So is SystemVerilog the future of mixed-signal modeling? It depends, Romaine said, on your background (analog or digital?) and what you're trying to achieve. Meanwhile, he emphasized, Cadence will continue to support wreal modeling with Verilog-AMS. This point was also made at a panel discussion at the Mixed-Signal Technology Summit held at Cadence Sept. 20, where there was a lively discussion about wreal, Verilog-AMS, and SystemVerilog.
Cadence Community members can access the free webinar here (quick and free registration if you're not a member). Cadence customers can read an app note here that shows how to write Verilog-AMS models that will be portable to SystemVerilog.
I have been doing discrete electrical modelling using VHDL for a number of years. I use record signal types and a Kirchhoff solver I wrote for resolution.
As I'm part of a multinational who has sold its sole to verilog and now also system verilog, I need to be able to migrate to SV2012 (or SV2013).
Who at Cadence can I work with to simulate (alpha or beta versions) of the tools and my models which I'll adapt to system verilog?
Also, I'd like to be able to netlist into the new SV2012 format. Today I achieve all I need using VHDL-Net but would hope to achieve similar using svnet. Probably adding some attributes to the virtuous database.
Today my flow is to model with VHDL. I then verify the transistor-level schematic using a VHDL testbench using AMS (and Spectre). I then also simulate the VHDL model against the same VHDL testbench using raw nc.
At the chip level the models are simulated using nc, vcs and questa.
Kevin: Thanks for giving your point of view; this might lead to an interesting discussion. Am I right to assume that you are the "simguru" who was discussing with Ken Kundert at www.semiwiki.com/.../video-interview-developer-spectre-circuit-simulator-1296.html ?
Dan: Thanks a lot for your detailed information. Could you give an estimate how much simulation time will increase if one uses SV UDT and UDR to model port impedances (assuming that this is possible)?
@Frank - the user-defined type support in SV is pretty dysfunctional and completely ignored what is done in Verizon-AMS. If Cadence supports wreal in SV, it's non-standard. Wreal in Verilog-AMS is also dysfunctional in that it doesn't fit in with rest of the type system. I.e. it may be fast, but it probably doesn't do what you want.
To answer your question Frank, there will be no difference in “functionally equivalent” code as both execute on the same event-based simulation engine. Looking at the details, RNM in Verilog-AMS generally consists of Verilog-2005 syntax and wreal module ports. The wreal ports are single-value real nets being used to connect two or more modules together. A user can create functionally equivalent code using the new SystemVerilog User Defined Types (UDT) and the associated User Defined Resolution functions (UDR). To do this, you could create a single-value real number nettype and associate it with one of the 6 built-in resolution functions (sum, average, minimum, etc.), giving you equivalent capability to Verilog-AMS wreals and running at the same speed.
How fast will the user-defined types and resolution functions of SystemVerilog simulate, compared to the pure RNM of Verilog-AMS?