Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
With nine technical paper presentations, six sponsored sessions, demos, and exhibits, Cadence will have a strong presence at ARM TechCon in Santa Clara, California Oct. 30-Nov. 1, 2012. Cadence papers and sessions will cover topics including advanced-node digital, mixed-signal, low power, verification IP (VIP), 14nm FinFETs, and embedded software development with virtual prototyping.
Cadence is also revving up for ARM TechCon with a pre-conference announcement of three successful verification projects using Cadence AMBA VIP. Representatives of CEVA, Faraday Technology Corp., and Hisilicon Technologies Co. Ltd affirmed how the AMBA VIP, which supports AMBA 4 protocols including ACE cache coherency, saved weeks or months of verification time. A press release provides more information about these engagements, and a new feature page on Cadence.com describes AMBA VIP and provides resources such as videos, articles, and blogs.
ARM TechCon is actually two conferences in one - a Chip Design Conference Tuesday Oct. 30, and a System and Software Design Conference Oct. 31 and Nov. 1. Here's what you can expect from Cadence during each of these conferences.
Chip Design Conference - Oct. 30, 2012
Exhibit: At Cadence booth #36, you can learn about an RTL-to-GDSII flow for ARM Cortex-A processors. Cadence will also demonstrate a mixed-signal solution for ARM Cortex-M0 based designs (for more information on this solution, see this recent ARM blog post).
Sponsored Sessions - Room #20410:30 - 11:20 Automating the verification of SoC interconnect fabricsHuzaifa Dalal, Senior Product Marketing Manager - VIP, Cadence and Mirit Fromovich, Staff Solutions Engineer, Cadence
11:30 - 12:20 Power efficient big.LITTLETM processing: lessons learned from a 28nm multi-core Cortex-A7 low-power implementation Paddy Mamtora, Group Director, Cadence
1:30 - 2:00 Designing with 14nm FinFET TechnologyLars Liebman, STSM, Distinguished Engineer, Design-Technology Co-Optimization, IBMVassilios Gerousis, Distinguished Engineer, Cadence
2:10 - 3:00 Implementing Advanced Next Generation Mali T6XX GPUs with Cadence Encounter Digital FlowsSanjiv Taneja, Vice President, Research and Development, Cadence
3:10 - 4:00 Designing mixed-signal with ARM CortexTM-M0 Luke Lang, Director of Engineering, Cadence
4:10 - 5:00 Optimizing Power Efficiency in GHz+ Quad-core ARM Cortex-A15 Processor Hardening
Technical Papers (click on links for details):
ATC-101 Tues @ 10:30amSilicon Validation of GLOBALFOUNDRIES-Cadence Digital Design Flow in 28nm using ARM Physical IP
ATC-103 Tues @ 10:30amAdvantages of NVMe for Low-Power StorageBob Pierce
ATC-106 Tues @ 11:30amBuilding Your UVM Environment for ACE-Based VerificationMirit Fromovich, Tamar Meshulum
ATC-112 Tues @ 2:10pmA Novel Power Intent Specification Methodology for the IP DeveloperJohn Decker
ATC-110 Tues @ 2:10pmCache-Coherent Interconnect Complexity, Verification, and Performance AnalysisNick Heaton, Stewart Penman, Paul Martin (ARM)
ATC-117 Tues @ 3:10pmImproving Performance, Power, and Area of a High-Speed Dual-Core ARM Cortex-A9‒Based SoC with Clock Concurrent Optimization TechnologyKoen Lampaert (Broadcom), Jason Corbisiero
ATC-123 Tues @ 4:10pmPCIe Gen 3 Implementation on AXIRaju Pudota
System and Software Design Conference -- Oct. 31 and Nov. 1, 2012
Exhibit: Cadence booth for these two days is #417. Demonstrations will include the System Development Suite and power-aware signal integrity analysis.
Sponsored Session: In room #212 Wednesday, Oct. 31, from 11:30 am - 12:30 pm, Cadence will offer a session titled "Prototyping and Early Software Development for ARM-Based Embedded Systems."
ATC-218 Wed @ 2:30pmImproving the Speed and Debug Ability of the Emulation/Prototyping Phase of ARM SoC DevelopmentLeonard Drucker
ATC-303 Thurs @ 10:30am Analysis of Software-Driven Power-Management Policies using Functional Virtual PlatformsMichele Petracca
ATC-323 Thurs @ 10:30am Fast-Track To Embedded Design With ARM Cortex-M0+ And Cadence Mixed-Signal IC Design FlowThomas Ensergueix (ARM), Mladen Nizic
For up-to-date information about Cadence at ARM TechCon, click here. For the ARM TechCon web site and registration information, click here.