Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
The next semiconductor process node after 20nm promises tremendous power and performance benefits, but also poses some new challenges, according to a presentation by ARM and IBM at the ARM TechCon conference Oct. 30, 2012. The presentation showed how the "second generation" of double patterning and the emergence of FinFET transistors will impact IC designers.
The presentation was authored by Lars Liebmann, IBM fellow and notable lithography expert, and Greg Yeric, principal design engineer at ARM. Unfortunately Liebmann was unable to attend due to Superstorm Sandy, so Yeric gave the entire presentation. Immediately after this presentation, a Cadence-sponsored technical session described a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM's FinFET process technology (see blog post about this session here).
Although the IBM-ARM talk was titled "Design and 14nm," Yeric first suggested that "10nm" is a more accurate descriptor. "What Lars means by 14nm is a pure node shrink of 20nm," he said. "It's a 70% linear pitch shrink, or a 50% area shrink, which may be renamed 10nm. What we're talking about is the next generation." Yeric referred to this node as "10nm" during most of the presentation that followed.
While many people hoped extreme ultraviolet (EUV) lithography would be ready for "what we'll now call 10nm," Yeric said, that's not going to happen - at least not for the development phase. He noted that EUV still has "an impressive list of things that have to be overcome," including a vacuum environment where particles can go all over the place, masks that can't have pellicles for particle protection, and the development of new resist chemistries, not to mention the need for a ten-ton crane to service an EUV machine on an ongoing basis.
From Double to Triple Patterning
According to Liebmann and Yeric, the "first generation" of double patterning is the Litho-Etch, Litho-Etch (LELE) approach used at 20nm today. Also called "pitch split," it works down to a 50nm to 60nm pitch. It's just like the name sounds - you expose the first mask, then etch; you expose the second mask, then etch. Colorization is used to determine which patterns go on which mask.
LELE double patterning requires "color aware" design tools, a double-patterning aware standard cell library, and new design rules. Even so, problems can emerge. These include what Liebmann calls "three body problems." Yeric explained: "If you have three things in a row that are in a tight pitch, you can't break them into two masks, so you have to identify the problem and understand how to fix it. In some technologies you can do stitching, where you overlap the two masks so they're electrically connected."
At the 10nm node, Yeric noted, pitches will be smaller than those allowed by LELE. So one alternative is triple patterning, which uses three colors and three masks. "It is a difficult problem for EDA, more than 50% harder - more like an exponential problem," Yeric said. "DRC [design rule checking] with 3 masks is an NP-complete problem." Thus, the challenge is to develop heuristics and algorithms that will permit the process to complete in a reasonable period of time, and work is ongoing to accomplish this.
While many potential first-generation double patterning problems could be avoided with cell design, errors will span across cells more frequently at 10nm, Yeric said. Triple patterning, he said, is "more of a systems issue." On the other hand, a third color can resolve many of the "three body problems" that occur when three shapes are too close together.
Self-Aligned Double Patterning
Another alternative that can be used at 10nm is Self-Aligned Double Patterning (SADP), also called Sidewall Image Transfer (SIT). This is a more complicated procedure than LELE - it involves creating relief patterns called "mandrels," depositing sidewall spacers onto the relief features, and trimming away everything that's not needed to produce the desired shape. The advantage is that it can work with pitches as small as 40nm, whereas LELE only goes down to 50nm to 60nm.
But as always, there are tradeoffs. Challenges of SADP include:
SADP is "still double patterning, but you get to where you want to go in a different manner," Yeric said.
Designing Cells with FinFETS
In a FinFET, the field effect transistor (FET) gate wraps around three sides of the transistor's elevated channel, or "fin." FinFETs provide more control over current than planar transistors, and promise greatly reduced power for a given level of performance. Yeric showed how FinFETs will allow transistor gate length scaling, which stopped around 90nm, to resume. The three-sided FinFET gate allows better control over leakage and provides a "good switch," he said.
Yeric pointed to other advantages of FinFETs, including improved sub-threshold swing, improved drain-induced barrier lowering, and lower channel doping, which enhances electron mobility and greatly reduces random dopant fluctuations. But FinFETs are not without challenges. One is "width quantization." Standard cell designers can make planar transistors any width they want, but they cannot change the height or width of a fin. They can add more fins to increase drive strength, but this, of course, can only be done in discrete increments (adding 1, 2 or 3 fins, not 2.75 fins).
A 12-track standard cell allows 12 fin pitches, but some of those pitches are needed for gate and rail connections, so you actually end up with 4 fins per device. That's probably okay. But an 8-track standard cell only leaves room for 2 fins per device, which is probably not sufficient for performance and variability requirements, Yeric said. Designers can adjust the number of fins by "pushing" the active fin pitch. For example, if the metal pitch is 48nm, fin pitches from 40nm to 48nm could be used, in combination with cell track heights from 8 to 13. This gives designers some flexibility but requires up-front planning.
"This design technology co-optimization discussion is another paradigm shift in this industry for FinFETs," Yeric said. "We didn't have to do any of this before. Now we need to have a discussion up front about the best plan of attack for what kinds of cells and fin pitches we need."
Designer's Cheat Sheet
At the conclusion of the presentation, Yeric offered a "Designer's Cheat Sheet" on FinFETs. Here's a brief summary:
--Local variation will decrease--On-chip variation (OCV) de-rating might be less optimistic--Less mismatch between device types--Reduced inverted temperature dependence (where things get slower as they get colder)
"The things we're talking about with FinFETs cross boundaries in the ecosystem," Yeric concluded. "We need design technology interaction, and we need design enablement discussions. There has to be a well functioning ecosystem to get the most out of FinFETs."
The Liebmann-Yeric presentation is available to ARM TechCon attendees; see the web site for details. Predictive FinFET models are available at http://ptm.asu.edu/.