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Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer these questions. This blog post reviews the first webinar in the series, which was offered Nov. 7, 2012 and has since been archived.
The webinar title is Understanding the "What If" to Avoid the "What Now." In the webinar Rama Jupalli, technical marketing manager for analog/custom design at Cadence, gives a good general overview of variation causes and challenges, corner analysis, statistical (Monte Carlo) analysis, and sensitivity analysis. Stacy Whiteman, senior customer engagement engineer at Cadence, provides a 20-minute demonstration of a sensitivity analysis flow.
Jupalli noted that there are many causes of variation - including temperature, manufacturing, device type, noise, device placement, voltage changes, design choices, and process nodes. This is nothing new for analog designers, he noted. "Having said that, when you move to advanced nodes at 45nm and below, the effects of variation are much more difficult to manage."
Why Variation Analysis is Mandatory
Why the difficulty? At 22nm, statistical effects can cause 20% in design losses, Jupalli said. Moreover, PVT (process-voltage-temperature) corners have doubled from around 25 at 65nm to nearly 50 at 22nm. Add in some design variables and different operating modes, and the result at 22nm may be hundreds of corner cases and thousands of simulations. Finally, it's not enough to just tape out at advanced nodes - you also have to meet yield requirements.
A typical corner analysis will look at 3-10 process corners combined with temperature and voltage sweeps. The intent is to find the problem corners and improve the design, and then re-run the corners before signoff. Jupalli talked about some of the ways that the Cadence Virtuoso ADE XLL corners analysis makes this process easier. For example, engineers can:
Another type of tool that's seeing increasing use at advanced nodes is statistical analysis, also called Monte Carlo analysis. Instead of forcing the design to specific corner case points identified by the foundry, it uses random distributions across the design space to detect failure regions. It closely mimics the production environment and lets designers view distributions, mismatch and device correlations. In the past, Jupalli noted, getting statistical models was difficult, but now most foundries provide statistical models.
Virtuoso ADE-XL Monte Carlo analysis provides the following features:
Why Sensitivity Analysis is Needed
While corner and analysis tools are reasonably fast, and provide valuable information, they still have limitations, Jupalli said. "You can see how the design is varying because of PVT corner changes, but having seen the results you won't be able to figure out exactly where the problem is, or which device or parameter is causing this issue. You won't be able to find the sensitivity of the design."
And that's where sensitivity analysis enters the picture. It allows designers to identify devices and parameters that need to be tuned in order to achieve desired performance. Designers can then do manual tuning or use optimization features in Virtuoso ADE-XL. Jupalli showed the following sensitivity analysis flow:
Stacy Whiteman's demo showed how engineers can use sensitivity analysis to find the parameters of interest in a design, and adjust those parameters so a design will meet specifications. She showed how to use statistical simulation to predict circuit yield, create statistical corners from the results of Monte Carlo simulation, and run optimization across the statistical corners.
"Corner tools and Monte Carlo tools are necessary but not sufficient to completely understand where the problem is in your design, and fix that problem," Jupalli concluded. "That's where sensitivity analysis and optimization come into the picture. At the end of the day, you'll have a robust design that will have a good yield."
Cadence Community members can access the webinar here (quick and free registration process if you're not a member).
Here are the subsequent webinars in the series. The Nov. 14 and Dec. 5 webinars are aimed at North America, with a start time of 9:00 am PST. The Nov. 20 and Nov. 27 webinars are aimed at EMEA, with a start time of 3:00 pm BET or 4:00 pm CET. To find out more and register, click on "Event details." Webinars are normally archived here within a week.
14 Nov 2012
Variation-Aware Design: Efficient Design Verification and Yield Estimation
In this webinar, we'll show you how to use advanced capabilities, such as worst-case corners and high-sigma yield analyses, to efficiently cover the design space and estimate design yield.Event details »
20 Nov 2012
27 Nov 2012
Variation-Aware Design: Detecting and Fixing Layout-Dependent Effects using the Virtuoso Platform
In this webinar, you'll see how advanced Virtuoso technologies can help you detect and fix LDE problems by rapidly producing layout and verification results that feed the industry's first LDE-aware design flow. Learn how to fine-tune the corrections necessary to make sure LDE problems don't stop you from getting your design manufactured on time.Event details »
05 Dec 2012