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Before digital SoC designers take advantage of the power, performance and density advantages of 20nm, custom/analog designers must develop the standard cells and the analog/mixed-signal IP. Thus, no 20nm solution is complete without an integrated custom/analog capability. A newly published Cadence whitepaper, Taming the Challenges of 20nm Custom/Analog Design, discusses design challenges and describes a new design methodology that's needed at this emerging process node.
The whitepaper provides details about challenges such as the following:
The whitepaper notes that the word "custom" includes different design styles with different care-abouts. For example, analog and I/O designers are most concerned about LDE, circuit specifications, and performance vs. area tradeoffs. Memory and standard cell designers are very concerned about density, and as such, double patterning and local interconnect are key concerns.
Double patterning requires a two-color layout decomposition process in which alternate colors, such as red and green, are used to indicate which features will be placed on which mask. Coloring conflicts are easy to create and hard to avoid. The use of an additional mask can cause mismatches, and mask shift during manufacturing is yet another source of variability. Placement, routing, extraction, and physical verification must all be double-patterning aware. Automated, color-aware layout, with rapid feedback on any errors, can greatly ease double patterning concerns for analog/custom designers.
Layout-dependent effects raise another challenge that can be confusing for designers. At 20nm, it's not enough to model the performance of a transistor or cell in isolation - where a device is placed in the layout, and what is near to it, can change the behavior of the device. As a result, circuit designers have to consider layout context as well as device topology, and they need to simulate with layout effects before a DRC-clean layout is completed.
Challenges such as double patterning, LDE, and new local interconnect layers cannot be solved with point tools. It's no longer viable for circuit designers to draw a schematic, run some simulation without layout effects, and toss it over the wall to layout engineers. What is needed is a new methodology in which circuit and layout designers exchange and share information, use "rapid layout prototyping" to provide early estimates of parasitics and LDE, and employ in-design signoff techniques that provide immediate feedback if a mistake is made.
The whitepaper uses the figure below to depict the kind of automated, collaborative methodology that's needed. Here, circuit designers develop constraints for layout engineers, and they run a pre-layout parasitic and LDE estimation. Both circuit and layout designers can use Modgens to automatically generate rapid layouts for structures such as differential pairs, current mirrors, and resistor arrays. These layouts allow accurate physical effects to be extracted, analyzed, and simulated.
The point in all this is that 20nm isn't just a tool change - it's a methodology shift as well. Certainly every tool in the custom/analog flow must be 20nm aware. But what's really needed is a methodology in which schematic and layout designers work in close cooperation, schematic designers run prototype layouts to gather parasitic and LDE information, and integrated signoff-quality engines provide instant feedback as the design is created. The end result is that the 20nm node will drive a much improved and more automated custom/analog flow, with benefits that ultimately apply to all process nodes.
For more details, you can download the whitepaper here.