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Cache-coherent interconnect is a key component of any SoC that uses the ARM AMBA 4 Coherency Extension (ACE) specification. It's hard to design and even harder to verify. A recently archived EE Times webinar shows why cache-coherent interconnect is so complex, and explains how to build a Universal Verification Methodology (UVM) based verification environment using verification IP (VIP).
The one-hour webinar was presented by Mirit Fromovich, verification IP solutions architect at Cadence. It was titled "How to Verify ARM ACE Coherent Interconnects with UVM Verification IP."
Fromovich began by noting that cache-coherent interconnect is more than just interconnect - it is also a coherency manager. "Unlike the AXI environment, where the interconnect just transfers data from one point to another, ACE based interconnect has a much broader responsibility," she said. For example, cache-coherent interconnect should be able to snoop the right master, calculate the accumulate response, make sure correct data is returned, perform speculative fetches to save time, and provide a "snoop filter" to avoid unnecessary access to processors.
Difficult to Verify
Going into more detail, Fromovich provided several examples of the complexity of cache-coherent interconnect. She showed how interconnect needs to manage multi-cache line operations, provide snoop filter support in the midst of a dynamically changing environment, and use barrier transactions to force ordering in the system. All these features, she said, "make cache-coherent interconnect much more complex and much harder to verify."
So, how can one build a verification environment that supports this complexity? UVM provides part of the answer. UVM, she noted, provides ease of use, scales to support large systems, offers block-to-system vertical reuse, and integration-ready components. She showed how UVM provides a configuration object that can greatly simplify the verification space.
Fromovich identified three key tasks that are required to verify cache-coherent interconnect:
She then showed how Cadence ACE verification IP (VIP) supports these requirements. As the following slide indicates, the solution includes a set of VIP "agents" including an active master that can generate stimulus, a passive master that can monitor bus transactions, and active and passive slaves that respond to read/write commands. The VIP also contains a cache model to ensure correct activity on the bus.
The Cadence VIP also supports what Fromovich called "intelligent transaction generation." Whereas AXI uses reads and writes, ACE transactions are much more varied and complex, she said. Further, each transaction is dependent on the cache state, and there are many possible permutations. Intelligent transaction generation considers four key factors - protocol constraints, timing between transactions, cache line state, and design-specific constraints.
Fromovich showed a complex scenario involving a "shared clean" cache state and a ReadShared transaction. She then walked through code examples for virtual sequences, a UVM capability for handling differing test sequences, and share/load transactions on a master, a way of simplifying tests by bringing a test scenario up to a higher level of abstraction.
For checking protocol compliance, using passive agents that sit on an individual master is not sufficient, she said. What's needed is an "Interconnect Validator" that can monitor activity for the entire interconnect, from block to subsystem to SoC. It is, in essence, "system VIP" that works with the VIP that verifies individual ports for compliance with the protocol specification. Cadence provides this capability.
Fromovich also discussed the UVM coverage model, and stressed the importance of filtering out illegal crosses so as to keep the verification space under control.
"It is not enough to just have ACE VIP that provides you with all the SystemVerilog sequences and constraints and coverage," she concluded. "It is a must to have an Interconnect Validator to ensure coherency. Without these two components you cannot get the completeness of your design."
This on-demand webinar provides a lot of good information for anyone interested in cache-coherent interconnect verification. You can access it here.