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One paradox of advanced node (28nm and below) custom IC design is that the layout "context" -what is placed near to a device - can change the performance of a device by as much as 30%. Thus, designers must be able to predict layout-dependent effects (LDE) before the final layout is completed. The Virtuoso Advanced Node design environment, introduced today (Jan. 28, 2013), makes this possible with a new methodology called "partial layout."
Virtuoso Advanced Node offers three new capabilities for custom/analog design - LDE analysis with partial layout, color-aware layout to support double or triple patterning, and support for new local interconnect layers located below the metal 1 layer. For more information about these challenges, see the recently published Cadence whitepaper Taming the Challenges of 20nm Custom/Analog Design. This blog post focuses on layout-dependent effects.
LDE starts to become an issue at 40nm, but it carries much more impact as process nodes decrease. At 28nm and below, it causes methodology challenges that ripple throughout the design flow. No longer is it sufficient to characterize a standard cell or device before layout, and accurately predict its performance in the circuit. No longer can circuit designers just draw a schematic and throw it "over the wall" to layout engineers. Designers need to account for LDE during circuit design, recognizing LDE as a third dimension of variability in addition to process and mismatch variation.
The example below shows how transistor gain is substantially impacted by well proximity effect (WPE), the variation in distance from a well. The expected transistor gain is the green line. However, if the transistor is built using the minimum design rule manual (DRM) rule set, you will fall short by 24.18dB. You need to increase the distance between Active and Nwell to achieve the desired gain. That means you will have to find the affected transistors and figure out how far to move them apart.
One solution to this quandary is partial layout. Steve Lewis, product marketing director at Cadence, said this methodology "allows us to go through a parameter extraction process before a full DRC/LVS clean layout is created. We're able to analyze the layout as the implementation is going, see what the layout dependent effects are going to be, and open a dialog between the layout designer and the circuit designer at the very earliest moments of the design."
In short, partial layout allows the circuit designer to discover which transistors are sensitive to LDE, put them in a layout, re-simulate with device parasitics, and quickly see if there is a problem. If so, the circuit designer can tell the implementation engineer that (for example) these transistors need more space, or need to be moved away from a well wall. This can happen very early in the design cycle. After that, Lewis said, "I'm checking things as I go. I build up my layout, and when I get to the final stages of full layout, I'm going to have a valid and perfectly working layout."
The graphic below shows how partial layout fits into the traditional custom/analog methodology. While MODGENs (automatic module generators) are a good way to look at constraints and generate quick layouts, they are not a requirement for partial layout. In-design verification, a theme that runs throughout the Virtuoso Advanced Node environment, provides rapid feedback as soon as errors appear.
The analysis of LDE in Virtuoso includes these two steps:
Virtuoso Advanced Node has new capabilities besides partial layout. Color-aware layout is a requirement for double patterning. Local interconnect layers can only be used by tools that comply with the appropriate design rules. But LDE is a particularly perplexing and problematic problem - how can you analyze a layout that hasn't been done yet? As Lewis said, "the design is more about the layout now than ever before."
Further information about Virtuoso Advanced Node is available in a feature story on Cadence.com.
Whitepaper: Taming the Challenges of 20nm Custom/Analog Design
Electronic Design article: Will LDE Stand Between You and Your Next Smart Device?
EDA DesignLine article: Electrically-aware design improves analog/mixed-signal productivity
Cadence Industry Insights blog: Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges
Cadence Industry Insights blog: ISQED Keynote: 20nm From a Custom/Analog Perspective
Hello Juergen - 20nm design rules are written so that the layout can be "decomposed" into two masks. The issue is not that the rules are not there, it is that many times, you will not know you violate the rule until you commit the current edit. Having a sign-off quality DRC check, in design, RealTime, is the solution. Virtuoso has a DRD engine for while you draw, and it can prevent most errors. But IPVS is the solution to ensure that the edit (given the amount of layout that exists) can be decomposed. If you want, send me a note? We can talk more about the topic. (my last name at cadence dot com)
I am designing in 180nm and cannot really understand this discussion. Design rules should be defined in a way, that effects of this kind are avoided at all. This is what I expect from a "design rule". Otherwise a design rule does not fulfill its obligation. Why aren't the design rules in 20nm and 28nm defined in such a way?? Can anybody explain?