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This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
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Whatever kind of design or verification work you do, CDNLive Silicon Valley 2013 will help you do it better. This Cadence user conference , set for March 12-13, 2013 in Santa Clara, California, will help you solve design challenges, discover the latest solutions and flows, and learn how other engineers are differentiating their designs. An agenda and registration information are available on line, and an "early bird" rate of $99 is available until Feb. 15, 2013.
CDNLive Silicon Valley 2013 features over 90 presentations from Cadence experts, partners, and customers. The conference also includes three keynote speakers, Designer Expo partner exhibits, lunches, and numerous opportunities for networking with other design and verification engineers. This year's conference also introduces a two-day PCB Track with sessions of interest to PCB designers.
Here's a more detailed look at what's happening during the two days of CDNLive Silicon Valley.
Paper sessions - 40 papers in the following tracks:
Lunch and Designer Expo
Paper sessions - 48 papers in the following tracks:
Lunch with Cadence R&D
Detailed information about CDNLive Silicon Valley, including abstracts for papers, is located here.
CDNLive events will also be held this year in Germany, Taiwan, Korea, Japan, China, India, and Israel, in addition to the U.S. east coast (Boston). For a complete calendar, click here.
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CDNLive! 2012 Proceedings - Over 150 User Presentations on Design and Verification