Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Do design and verification engineers care about EDA standards? If the Accellera Systems Initiative "Town Hall" meeting at DVCon 2013 Feb. 25 is any indication, the answer is an emphatic yes. A packed audience attended a lively, hour-long meeting in which non-stop questions were answered by Accellera and IEEE standards developers.
The meeting was chaired by Accellera board member Yatin Trivedi (Synopsys), with frequent commentary from standards participants including Stan Krolikoski (Cadence), Tom Alsop (Intel), Dennis Brophy (Mentor), Martin Barnasconi (NXP), John Brennan (Cadence), Warren Stapleton (AMD), and others. Topics included updates on existing standards efforts as well as more philosophical issues, such as whether "paper based" standards are obsolete in this era of the Internet.
Accellera Town Hall meeting at DVCon 2013
There was some news to start the meeting. Karen Pieper (Tabula), technical chair at Accellera and also chair of the IEEE 1800 SystemVerilog working group, announced that the new SystemVerilog 2013 standard (IEEE 1800-2013) has been released for general availability. She said the two biggest improvements are better support for assertions and for digital/analog to digital signal connections in simulation. The new standard is available for free download from the IEEE. Further information is in an Accellera press release.
Some Questions and Answers
Q: Is there a schedule for UVM 1.2?
Tom Alsop, co-chair of Accellera VIP Technical Subcommittee: "It's not solidified on when it will be released. We were originally targeting DAC but we are trying to resolve the run-time phasing issue. Getting phasing up and running is more important than anything else."
Tom Fitzpatrick (Mentor): What's happening with run-time phasing is that there are two competing APIs in the committee. Run-time phasing is not going away.
Q: Accellera is doing standards work and is also developing a software base class library for UVM. How do you balance that dichotomy?
Stan Krolikoski, Accellera secretary: There are three types of standards organizations. One is a pure standards body with paper standards, such as the IEEE or IEC. A second model is an open-source software development organization. Thirdis a hybrid model. That's where Accellera fits. It is primarily a standards body, but UVM does have a reference implementation and IP-XACT has an XML schema.
The UVM reference implementation is done under an Apache 2.0 license. It's open source. But the API for UVM does not change; it is "fixed and locked" until the committee decides otherwise.
Yatin Trivedi: "That distinction is very important. You would not want multiple APIs floating around, each one touting itself as the standard."
Q: What is the plan for UVM to support multiple languages like e and SystemC, in addition to SystemVerilog?
Warren Stapleton, Accellera director: "There is an ongoing effort to come up with a mixed language solution. We've collected about a half dozen companies who have aligned on a set of user-level requirements for a solution. We'll gather further vendor and user company requirements and lead with that."
Q: When will IP-XACT support analog/mixed-signal?
Martin Barnasconi, Accellera director: An Extensions Working Group, which is a sub-group of the IP-XACT Technical Subcommittee., has developed metadata definitions to deal with continuous time as well as discrete time semantics. These will be standardized extensions.
Q: "I think we need to come up with new paradigms for developing standards that are not paper based and are more interactive." It took 2-3 years to turn IP-XACT around, 3-5 years for SystemVerilog, a "very long time to wait. You could do it at a micro-level where every few days there's a new release, like Linux."
Krolikoski: "A passion of mine is that we have open standards, but that means open to anyone who meets membership criteria, not open so they can change every few days. Companies need a fixed document they can work with...having said that, the notion of a static PDF document is probably an outdated way of presenting a standard."
Dennis Brophy, Accellera vice chair: The IEEE is attempting to move down a path that will allow easier web-based access to information. The goal is a "more live feel" to documents.
Stu Sutherland, consultant: "PDF is portable but not very searchable. I would like to see a much more web-based and very portable version."
Q: Is there an initiative that would provide a consistent coverage database format for code coverage and functional coverage?
John Brennan: "I've been working on UCIS [Unified Coverage Interoperability Standard] for four years now, and that API exists. It works really well for functional coverage. With code coverage, every vendor has a different implementation, so the level of interoperability is less than perfect."
Brophy: There's a [UCIS] API but there isn't an underlying common database. We're leaving that to the tool developers so they can develop the best database for their application.
EDA Standards Efforts Need You!
The meeting concluded with a call to users to get involved with standards. Addressing a second question about code coverage, Shishpal Rawat (Intel), Accellera chair, said "I think it would be very helpful if you could join the committee and contribute your ideas." Krolikoski followed up by noting that a number of user companies have recently joined Accellera. "If we're already in the same ballpark, come on over, you're welcome. And if we're not doing it, propose it."
To learn more about the Accellera Systems Initiative and membership criteria, click here.