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Systems on chip (SoCs) are incredibly varied, extremely complex, and based on rapidly changing requirements and specifications, according to Martin Lund, senior vice president for R&D at the Cadence SoC Realization Group. At a keynote speech at the CDNLive Silicon Valley conference March 12, 2013, he noted that traditional approaches to "IP reuse" need to give way to IP that's optimized for the application requirements of the SoC.
Held in multiple locations throughout the year, CDNLive is the Cadence user conference. CDNLive Silicon Valley ran March 12-13, and it drew over 800 attendees for around 100 technical sessions. Keynote speeches were given by Lip-Bu Tan, Cadence president and CEO (blog post here); Young Sohn, president and chief strategy officer for device solutions at Samsung Electronics (blog post here); and Martin Lund.
SoCs are everywhere, Lund noted - smart TVs, self-driving cars, Google Glasses, and more - and all have different capabilities and requirements. At the same time, standards are changing frequently and are getting more complex. "My favorite is the PCIe Gen 3 spec with 860 pages, full of requirements that all have to work," Lund said. Add in the cost factors of verification and IP integration, and it's no wonder SoC development is "under stress."
Rethinking IP Reuse
Lund noted that Ethernet, regarded by some as a "boring protocol," has gone through 45 changes over the past three decades. This rate of change "means the IP reuse model is under stress," he said. "You cannot rely on building it once and reusing many times. Rapid changes in standards, technology, new processes, and constantly changing requirements make IP reuse difficult. We have to design for changes."
Furthermore, what's often forgotten in "chip land" is the software portion, Lund noted. "We have to design with the software in mind, and the IP that resides in the blocks has to be optimized from a software perspective, a power perspective, and a performance perspective."
As he has in previous talks, Lund described the "old ways" of doing IP business. These include the IP Bazaar, where price and availability are the key concerns, and the IP Mall, where one can buy an off-the-shelf standard building block that may or may not fit the SoC. In a "next generation" IP approach, in contrast, "we build the IP to the requirements of the SoC. It's built with a quality focus as our number one target, and optimized for integration and software implementation. You get what you need for your SoC - not more, not less."
This next-generation IP approach has a proven track record already - Cadence has delivered over 3,100 DDR controllers using this approach, Lund noted. "Our portfolio is not just about building blocks, it's about putting together the subsystems, pre-verifying them, and building them correct by design."
Speaking briefly of the March 11 announcement of a Cadence agreement to acquire Tensilica, Lund said that the "intelligent and optimized subsystems they [Tensilica] put together will allow us to deliver more optimized IP for the target market you are building your SoC for."
In February 2013 Cadence announced an agreement to purchase Cosmic Circuits, a provider of analog/mixed-signal IP. Lund said that Cosmic offerings "nicely complement" Cadence high-end protocol IP. Tensilica IP, meanwhile, "sits smack in the middle of an SoC to provide the intelligent application of functions for baseband, audio, processing, image processing, or DSP capabilities."
Lund concluded his talk by noting that Cadence offers the broadest portfolio of verification IP (VIP) in the industry and supports all vendors, simulators, and languages. "We're building next-generation IP and VIP to help you get to market faster. We want to generate the optimal configuration, and allow it to be changeable and flexible to prolong the life cycle of your product," he said.
For blogs, tweets, pictures and reports from the conference, see the CDNLive Multimedia page.
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Lip-Bu Tan at CDNLive 2013: Opportunities and Challenges for Electronics, and How Cadence Can Help
Samsung CDNLive Keynote: Innovation and Challenges in the Post-PC Era