Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Systems on chip (SoCs) are incredibly varied, extremely complex, and based on rapidly changing requirements and specifications, according to Martin Lund, senior vice president for R&D at the Cadence SoC Realization Group. At a keynote speech at the CDNLive Silicon Valley conference March 12, 2013, he noted that traditional approaches to "IP reuse" need to give way to IP that's optimized for the application requirements of the SoC.
Held in multiple locations throughout the year, CDNLive is the Cadence user conference. CDNLive Silicon Valley ran March 12-13, and it drew over 800 attendees for around 100 technical sessions. Keynote speeches were given by Lip-Bu Tan, Cadence president and CEO (blog post here); Young Sohn, president and chief strategy officer for device solutions at Samsung Electronics (blog post here); and Martin Lund.
SoCs are everywhere, Lund noted - smart TVs, self-driving cars, Google Glasses, and more - and all have different capabilities and requirements. At the same time, standards are changing frequently and are getting more complex. "My favorite is the PCIe Gen 3 spec with 860 pages, full of requirements that all have to work," Lund said. Add in the cost factors of verification and IP integration, and it's no wonder SoC development is "under stress."
Rethinking IP Reuse
Lund noted that Ethernet, regarded by some as a "boring protocol," has gone through 45 changes over the past three decades. This rate of change "means the IP reuse model is under stress," he said. "You cannot rely on building it once and reusing many times. Rapid changes in standards, technology, new processes, and constantly changing requirements make IP reuse difficult. We have to design for changes."
Furthermore, what's often forgotten in "chip land" is the software portion, Lund noted. "We have to design with the software in mind, and the IP that resides in the blocks has to be optimized from a software perspective, a power perspective, and a performance perspective."
As he has in previous talks, Lund described the "old ways" of doing IP business. These include the IP Bazaar, where price and availability are the key concerns, and the IP Mall, where one can buy an off-the-shelf standard building block that may or may not fit the SoC. In a "next generation" IP approach, in contrast, "we build the IP to the requirements of the SoC. It's built with a quality focus as our number one target, and optimized for integration and software implementation. You get what you need for your SoC - not more, not less."
This next-generation IP approach has a proven track record already - Cadence has delivered over 3,100 DDR controllers using this approach, Lund noted. "Our portfolio is not just about building blocks, it's about putting together the subsystems, pre-verifying them, and building them correct by design."
Speaking briefly of the March 11 announcement of a Cadence agreement to acquire Tensilica, Lund said that the "intelligent and optimized subsystems they [Tensilica] put together will allow us to deliver more optimized IP for the target market you are building your SoC for."
In February 2013 Cadence announced an agreement to purchase Cosmic Circuits, a provider of analog/mixed-signal IP. Lund said that Cosmic offerings "nicely complement" Cadence high-end protocol IP. Tensilica IP, meanwhile, "sits smack in the middle of an SoC to provide the intelligent application of functions for baseband, audio, processing, image processing, or DSP capabilities."
Lund concluded his talk by noting that Cadence offers the broadest portfolio of verification IP (VIP) in the industry and supports all vendors, simulators, and languages. "We're building next-generation IP and VIP to help you get to market faster. We want to generate the optimal configuration, and allow it to be changeable and flexible to prolong the life cycle of your product," he said.
For blogs, tweets, pictures and reports from the conference, see the CDNLive Multimedia page.
Related Blog Posts
Lip-Bu Tan at CDNLive 2013: Opportunities and Challenges for Electronics, and How Cadence Can Help
Samsung CDNLive Keynote: Innovation and Challenges in the Post-PC Era