Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
IC design teams can use one of two formats to express power intent - the Common Power Format (CPF) from the Silicon Integration Initiative (Si2), or IEEE 1801, also known as the Unified Power Format (UPF). Efforts are now underway to bring the two formats closer together, and Qi Wang, technical marketing group director at Cadence, is at the center of that activity. Most recently, he's been involved with the new IEEE 1801-2013 (UPF 2.1) standard, which was approved by the IEEE RevCom (Review Committee) March 6, 2013.
In this interview Wang discusses what's new in IEEE 1801-2013, what Cadence and Si2 contributed, why "methodology convergence" is important, whether a single format will someday emerge, and how these formats can address power intent at the system level.
Q: How long have you been working on power format standards, and what's your role today?
Wang: In 2005 I started working on a power format within Cadence. I then led a cross-product team of architects to work on this new format to enable a low-power flow from RTL to signoff. After the contribution of the format to Si2 in 2006, I became the chair of the Format Working Group of the Low Power Coalition of Si2. Based on the format contribution, Si2 released CPF 1.0 in 2007, followed by CPF 1.1 in 2009 and CPF 2.0 in 2011. Starting in 2011, I've also been representing Cadence in the IEEE 1801 working group.
Q: The previous version of IEEE 1801 was IEEE 1801-2009 (also called UPF 2.0). How is the new IEEE 1801-2013 standard different?
Wang: The new version is significant in several ways. First of all the IEEE 1801 working group represents a significant number of user companies, much more than the working group for the 2009 version. It's pretty much a user-driven committee, targeting real low power design challenges.
The second aspect is that the standard is significantly improved. It deprecates a lot of outdated constructs from the old Accellera UPF 1.0 standard and it clarifies many ambiguities in the IEEE 1801-2009 version. It has quite a few new commands and options, as well as some new concepts such as equivalent supplies. In some cases, it also introduces new semantics for existing commands and options. It also leverages the contribution of CPF 2.0 from Si2, which resulted in a set of new commands in this new version that describe hard IP power intent and power management library cells.
Finally, the new version includes more examples to make it easier for designers to use this new standard in production designs.
Q: What did Cadence contribute to the new standard?
Wang: First of all, we have been an active participant of almost all working group meetings since 2011, and have been working closely with other members on many aspects of this new standard. In addition, Cadence also contributed three documents to IEEE for the purpose of developing this new standard. One illustrates a recommended low power design methodology using IEEE 1801 in a hierarchical flow. Another shows how to use the new commands to model power management library cells, like isolation cells and retention cells. That means you no longer have to rely on Liberty [an open source library format] for power cell command attributes with the new standard. The third document shows how those library cell commands can be correlated to Liberty attributes.
Q: You've talked about "methodology convergence" as the first step towards format convergence. Why is that?
Wang: A format is just a format. In reality, people doing designs follow a flow that dictates how the format is being used. Even with the same format, if people use it differently, it can put different requirements on the tool support of the format. That makes it very difficult for EDA companies to support the format.
With methodology convergence, we can define a subset of the commands so that multiple EDA vendors can enable a true multi-vendor flow. Without a common methodology we cannot enable a flow, even with the same format.
Q: How have UPF and CPF methodologies been different in the past?
Wang: One example is that the Accellera version of UPF 1.0 required the specification of power and ground nets even at the RTL stage. However, in IEEE 1801-2009 and CPF we can specify power intent at RTL without even mentioning power and ground nets. Specifically, in CPF the primary object is the power domain and the supply net specification is not needed at RTL. If you look at UPF 1.0, it is supply driven. Because of that it is sometimes hard to describe a particular low power technique, such as body biasing.
Q: Wasn't IEEE 1801-2009 an improvement from a methodology convergence standpoint?
Wang: Yes, but all constructs from UPF 1.0 were added to the final version of IEEE 1801-2009. So even though the intended new methodology of IEEE 1801-2009 very much complied with CPF, the addition of UPF 1.0 made it very confusing and hard to adopt. That's why part of the objective of the 2013 version is to deprecate many of those outdated constructs from UPF 1.0.
Q: Do you think we'll ever get to one power intent format?
Wang: As we said two years ago, the industry must achieve methodology convergence first before format convergence. The release of the new 1801-2013 standard is a great testimonial of that. The fact that the new version has so many significant features, including contributions from CPF, shows that one format is definitely a possibility. But we are not there yet even with the release of IEEE 1801-2013. There are still some CPF features that are not in IEEE 1801-2013, and that's what we will work on next.
Q: Both CPF and IEEE 1801 are primarily aimed at RTL-to-GDSII design. Will these formats, or a future converged format, address system-level power intent?
Wang: That's a very active topic in the Si2 Low Power Coalition. The Si2 Format Working Group and Model Working Group are exploring what can be done to extend power intent to the system level. Currently we have identified several places where the format needs to be extended to support such a flow, and we expect a future revision of CPF will address system-level modeling requirements. To my knowledge, this subject is also being discussed at the IEEE 1801 working group as it is working on a roadmap for the next couple of years.
The industry has converged from many formats to two, and is on the way from two to one. So maybe the two sides can collaborate on system-level modeling. It's a very good topic.
Related Blog Post
Video: What the Newly Approved IEEE 1801-2013 Low Power Format (UPF 2.1) Includes