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Why is there a need for "best practices" in mixed-signal SoC verification, and what are some of those practices? A presentation at the recent DVCon 2013 conference addressed these questions by showing how Maxim Integrated is bringing digital techniques into mixed-signal verification. Here's a brief description of the presentation and a short video interview with one of the co-authors, Neyaz Khan of Maxim. (The paper is available to DVCon attendees here).
The paper is titled "MS-SoC Best Practices - Advanced Modeling & Verification Techniques for First-Pass Success." Authors include Khan, distinguished member of technical staff at Maxim; Greg Glennon, principal member of technical staff at Maxim; and Dan Romaine, staff solutions engineer at Cadence.
The presentation was given by Glennon, who first noted that mixed-signal verification has many challenges - including connectivity/interconnect bug escapes, digital/analog interaction bug escapes, spec-versus-functionality mismatches, and lack of clearly defined verification metrics. To solve these challenges, Maxim is adopting proven techniques from digital verification. These include verification planning, analog and digital coverage metrics, constrained-random stimulus, automated checkers with assertions, and structured testbenches.
Glennon showed how real number modeling allows high-speed simulation of analog blocks, without the performance limitations of analog solvers. He also discussed mixed-signal metric driven verification (MS-MDV), the application of the Universal Verification Methodology to mixed-signal (UVM-MS), and plan-driven verification. Although Maxim is bringing these "digital" techniques into mixed-signal verification, the analog designer's job really doesn't change - he or she is still designing analog blocks using the same tools and methodologies as always.
In the video, Khan describes why standardized methodologies are needed for mixed-signal SoC verification. He identifies some of the challenges, and describes practices that can help, including verification planning and UVM-MS. He also notes that analog designers continue to design blocks as they always have. "When people look at what we are doing, and how it builds on top of the quality they are providing, they embrace it," he notes.
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