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A presentation at the DesignCon 2013 conference illustrated a new methodology that speeds timing closure for ASIC and SoC designs with hundreds of millions of gates. Called "multi-level physical hierarchy design," it overcomes many limitations of conventional "two level" hierarchical flows. The GigaScale option in the Cadence Encounter Digital Implementation System supports this new methodology.
Here's some quick background. Synthesis and layout optimization for timing closure are flat in nature, meaning that the entire design is treated as one physical entity. These optimization methods consume more and more memory, and require longer run times, as chip designs get bigger. As a result, high-performance multi-million gate designs today are commonly optimized by partition-based hierarchical methods. These approaches divide a large chip into sub-chips or partitions that are small enough to be optimized as a flat design.
With a conventional two-level physical hierarchy flow, each partition can be further divided into more partitions. However, hierarchical design flow steps - such as feedthrough (for managing channel congestion), pin assignment, and timing closure - are accomplished one level at a time, potentially leading to sub-optimal results. For example, pin assignments made from observing just one level of hierarchy could lead to infeasible floorplans.
One Run, All Levels
This is where the new multi-level physical hierarchy approach comes in. With this "nested partition" methodology, partitions across all levels of physical hierarchy are specified with their fence boundaries. Optimization steps such as feedthrough, pin assignment, and timing budgeting are done for all levels in one run. For example, feedthrough is done by looking deep into the nested partitions and adding feedthrough paths and buffers.
In the diagram below, shown at DesignCon, we can define P1 and P2 as physical partitions; we can define either P4 or C1 as physical partitions; and we can define either P3 or C2 or G1 as physical partitions. The floorplan representation is shown at the left.
In the DesignCon presentation Kamalpreet Singh, member of consulting staff at Cadence, talked about the motivations for multi-level hierarchical design. "In order to design multi-million gates, it is impossible to implement a chip in just four modules," he observed. Since chips have so much complexity, he said, it is necessary to parallelize work across different design teams, preserve the hierarchical nature of designs, and reduce tool run times.
Singh walked through the multi-level hierarchy flow supported by the Encounter Digital Implementation System, including these steps:
The illustration below shows how a multi-level unaware router might handle routing of a partitioned design (left), as compared to a trial router that is aware of physical hierarchy at multiple levels (right).
Proof in Silicon
Singh discussed a customer test design that used a multi-level hierarchical flow. It was a 40nm chip with a Cortex-A9 quad core design. There was one partition at the top level and four partitions inside of that - CPU0, CPU1, CPU2, and CPU3. Singh presented a "nested partitions" flow that included defining partitions, place and route, pin assignment, timing budgeting, committing and saving partitions, and assembling data.
In conclusion, Singh noted, the multi-level physical hierarchy flow allows feedthrough, pin assignment, and budgeting for all levels at "one go;" provides better quality of results for pin assignments and accurate timing budgets across different partition levels; and helps to identify congestion and timing hotspots. It works for all types of designs and provides a significant turn-around time reduction.
The paper is titled Multi-Level Hierarchical Flow for Giga Scale ASIC Designs. Singh's co-authors for the DesignCon paper are Sashank Prasad of Cadence and Matthias Andersch of Renesas Electronics Europe.