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Can the same SystemC TLM2 models be used in virtual platforms and high-level synthesis? Today the answer is typically "no." However, there is a "middle ground" modeling methodology that can turn this "no" into a "yes," according to Stuart Swan, senior architect at Cadence. Swan gave a presentation on this topic at DVCon 2013, and in the short video clip below he recounts some of the highlights.
Swan spoke at a Monday Feb. 25 tutorial titled Increasing Productivity with SystemC in Complex System Design and Verification (a video recording of his presentation is available here). He noted that the ability to synthesize SystemC TLM2 models would result in a "dream" flow that would permit a single, high-level "golden model" for SoC blocks. A single model could be used for software development with a virtual platform and hardware implementation with high-level synthesis.
The reason this typically doesn't happen is that the SystemC TLM2 standard was not designed for synthesis - it was intended for modeling virtual platforms at near real-time simulation speeds. High-level synthesis has modeling requirements that are not typically met by TLM2. For example, high-level synthesis modeling uses finite state instead of dynamic memory allocation, and requires careful and limited use of pointers.
In the tutorial, Swan outlined a "middle ground" that works for both virtual platforms and high-level synthesis. Key aspects include a minimal number of processes, a process and memory structure that properly reflects hardware architecture, and the use of synthesizable TLM interfaces. Swan showed how a single-source SystemC model can be automatically configured for TLM2 or for high-level synthesis.
In the video, Swan talks about why design teams want a unified modeling flow, what has prevented that in the past, and how the "middle ground" methodology works. If video fails to open, click here.
In addition to this video, a number of other short video clips from DVCon 2013 are available for viewing. Links are provided below.
DVCon 2013 - Tutorial: Fast Track your UVM Debug Productivity with Simulation and Acceleration
DVCon 2013: Interview with Oski Technology CEO Vigyan Singhal
DVCon 2013: Interview with AMIQ CEO Cristian Amitroale
DVCon 2013: Best Practices in Verification Planning
DVCon 2013: AXI Asynchronous Bridge Verification with AXI ABVIP and Formal Datapath Scoreboards
DVCon 2013: Saurabh Shrivastava of Xilinx on paper "How to Kill 4 Birds with 1 Stone Using Formal"
DVCon 2013 - Meirav Nitzan of Xilinx on her poster "A Smart Generation of Design Attributes"
Interesting topic. Would be great to reuse the same models for virtual prototyping and HLS. The presentation highlights the different requirements for both use cases and proposes a methodology for configuring the models accordingly.