Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
There's a lot of excitement about the use of FinFETs at advanced process nodes, and no wonder, given their potential power and performance advantages over planar transistors. But CAD and methodology challenges remain, particularly when it comes to parasitic extraction. FinFET extraction challenges received a thorough review at the recent Electronic Design Process Symposium (EDPS) in a presentation by Tom Dillinger (right), CAD Technology Manager at Oracle.
Dillinger's talk was part of a "Foundry Day" on FinFETs at EDPS, a small but influential IEEE workshop that brings together some of the world's top experts in electronic design methodologies. The day was organized by Dan Nenni, founder and blogger at SemiWiki.com. Aparna Dey, senior technical marketing manager at Cadence, moderated the morning session that included Dillinger's talk. You can view the entire two-day EDPS program, and download presentation slides, here.
In an introductory talk, Nenni gave a brief overview of the FinFET value proposition, design challenges, and added complexities in terms of growing design rule manuals. Compared to planar transistors, performance is expected to increase 10-20% for the same power, or power is expected to decrease 25-40% at the same performance. Challenges include power density per unit, layout-dependent effects, new sources of process variation, new analog structures, and EDA tool challenges. "There are significant challenges, but the value proposition for FinFETs justifies the extra effort," Nenni said.
A Detailed Look at Extraction
Dillinger's presentation provided a FinFET transistor overview, discussed parasitic FinFET elements, and noted the challenges of extracting a FinFET parasitic model. Topics included the topology of the vertical fin and its impact on extraction; dummy gates and their impact; gate input capacitance and gate input equivalent resistance; advantages and shortcomings of the BSIM-CMG model; and the need to extract a reduced, equivalent electrical model.
Here are some of the takeaways from the presentation.
How FinFETs are made. Using a technique called "sidewall image transfer," a silicon fin is constructed through an anisotropic etching of a silicon layer, defined by a spacer deposited over a "sacrificial" patterned layer. Fins are always fabricated in pairs, so if an odd number of fins are required, a fin will need to be cut.
Fin profile is very important. Fins with a "rounded" profile are easier to fabricate, but introduce additional parasitic extraction challenges. Fin profile also affects leakage current substantially. Fins with very sharp, rectangular profiles lose some of the sub-threshold leakage savings promised by FinFET technology.
Sources of variation in FinFET geometry. These include fin height, fin thickness, fin corner rounding profile, fin sidewall roughness, gate line edge roughness, and gate CD variation over multiple parallel fins.
No body effect - good for digital, maybe not for analog. Since fins are fully depleted, there is very little body effect (Vt dependency on substrate bias). Digital designers see the body effect as detrimental and will welcome its disappearance. Some analog designers, however, make use of the body effect to tune transistor performance.
FinFET source and drain resistances are high. One cause is the use of a very narrow fin that is very lightly doped. To reduce Rs and Rd, an existing fabrication method called "selective epitaxial growth" can increase the volume of the source and drain regions.
BSIM-CMG model for FinFETs sets the standard. With BSIM-CMG, we have a standard model for FinFETs, and SPICE developers can start creating models. "We are full speed ahead on circuit simulation for FinFET technology."
But, BSIM-CMG model has some shortcomings. It uses an ideal single-fin model, which you simply multiply by the number of fins and fingers - this may be "a little deficient going forwards." BSIM-CMG model does not yet include layout-dependent effects.
Dummy gates are required for FinFET fabrication. This impacts parasitics, and makes it harder to migrate planar device layouts (which do not require dummy gates) into FinFET layouts.
New parasitic capacitances need extraction and modeling. 3D structures contribute to gate-to-source capacitance (Cgs), gate-to-drain capacitance (Cgd) and gate-to-substrate capacitance (Cgx). "I get great drive strength improvement, but I also have an increase in parasitic gate input capacitance as well. This is a big detraction for very high performance applications."
What model is needed for equivalent gate input resistance? The BSIM-CMG developers at U.C. Berkeley haven't accounted for gate resistance yet. "If this matters to you, FinFETs are still a work in progress."
A big issue from a design perspective is reduction. We have to reduce a tremendous amount of parasitic information into an equivalent electrical model that can be annotated to a designer's schematic. "Talk to your EDA vendor about extraction and parasitic reduction."
Parting comment: "I'm not worried as much that variation is going to blow up. The actual fin topology has a big impact on sub-threshold behavior, on parasitics, and on modeling. So you have to characterize it and give it to the technology file that the designers use when they abstract. That's the big one."
Slides from Dillinger's presentation are available here.