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The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design Automation Conference (DAC 2013) Tuesday, June 4 from 8:00 am to 10:00 am.
The breakfast focuses on the Cadence System Development Suite, a set of four interconnected engines for virtual prototyping, simulation, acceleration/emulation, and rapid FPGA prototyping, with links to advanced verification with the Incisive simulation environment and Cadence Verification IP. The suite supports hardware/software co-verification at various points in the design cycle. At the breakfast, you'll learn more about the various engines and how they're used, and you'll hear about recent improvements such as in-circuit acceleration and hybrid use models combining the various engines.
Most importantly, the event will feature a panel that includes several System Development Suite users. As of this writing, panel participants are:
These panelists will talk about how they apply the different technologies such as virtual prototyping, RTL simulation, in-circuit acceleration, acceleration, emulation, and rapid prototyping to optimize verification efficiency for their designs. Audience questions will be very welcome, so bring your toughest questions.
"The main objective is really to have people understand system-to-silicon verification and put that in perspective with what customers are doing," said Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group and organizer of the breakfast. He said that attendees will "walk away with a better understanding of the sweet spots of the different engines in the System Development Suite and how they can be combined to achieve even greater improvements."
But first, you have to register - and space is limited. Click here for registration and further information.