Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Keynote speeches at electronic design conferences tend to focus on high-level industry issues. The "Designer Keynote," part of the Designer Track at the recent Design Automation Conference (DAC 2013), was different. In engineer-to-engineer talks, design managers from Qualcomm and Texas Instruments discussed challenges and solutions for designing mobile communications systems-on-chip (SoCs).
The first speaker was Scott Runner (right), vice president of advanced methodologies and low-power design at Qualcomm. He spoke about SoC design for mobile applications, particularly smartphones. The second speaker was Sanjive Agarwala, TI fellow and director of worldwide silicon development at Texas Instruments. He focused on the design of mobile infrastructure processing systems from a base station point of view.
Both reached essentially the same conclusion - whether it's an SoC for a cell phone or a base station, it's a system-level problem that needs system-level solutions.
Mobile SoC Processor Challenges
Runner started his talk by pointing to the complexity of smartphones today. Far more than phones, they are "integrated platforms for providing seemingly disparate technologies that have come together to provide a new user experience." What is required to create such a device? "The heart of it is a mobile SoC processor that must be married together with power management ICs, with RF, sensors, display, and battery, into a small form factor that has to be light and low cost," Runner said.
Runner identified three key challenges in smartphone design - low power, verification/validation, and hardware/software co-design. Illustrating the power challenge, he showed a plot of the relative performance increase of the CPU, GPU, and memory bandwidth over time, compared to the power savings provided by process node shrinks. Conclusion: "Process scaling is insufficient to support the increase in performance that's required to enable all these exciting new applications."
Runner noted that there's a tremendous amount of "feature growth" in smartphones today, translating into a demand for performance and memory. And yet, designers have a thermal envelope with a limitation of 4 or 5 watts (compared to about 20 watts for a laptop). Battery technology is not keeping up with the increasing demand for power consumption.
DAC chair Yervant Zorian (right) presents Scott Runner with an appreciation certificate following Runner's talk.
How can we solve the power problem? "First and foremost, we must realize this is a system design problem," Runner said. That requires an awareness of system architecture, workload partitioning, hardware/software partitioning, and power modeling and optimization. Also, there's a need for effective power management strategies - such as dynamic CPU and GPU control, dynamic voltage and clock scaling, and power gating. Designers need to determine where return on investment is best.
Complex Verification Task
Runner's second challenge was verification and validation, and he noted the difficulty of validating complex system-level scenarios. And it's not just a matter of finding functional errors. "I have to pay attention to performance and security validation, power validation, regulation and conformance testing, interoperability and field testing, compliance and qualification testing, and user interface testing," he said. And to top it all off, process variability is on the rise.
The solution, again, is working at the system level. That means validating the architecture at a high level of abstraction, and re-using verification and validation throughout the flow. It also calls for a variety of engines including simulation, formal verification, acceleration, and emulation, since all have different performances and timeline requirements.
The third challenge, hardware/software co-design, is driven by a realization that "software is growing faster than hardware" and is experiencing a state space explosion of its own. Runner takes a realistic view: "Do I expect hardware and software teams to use the same tools, to be on the same design timelines, to use just one model abstraction? No. I see collaboration between hardware and software teams in terms of documentation and specifications and the overall platform."
Challenges of the Infrastructure
To use mobile communications devices, you have to have an infrastructure that supports them, and that's what Agarwala (left) oversees. He first noted the complexity of embedded systems such as base stations and the myriad of requirements they must meet - not only power and performance, but also safety and reliability. "Putting all this together is the crux of being able to grow in this industry," he said.
Agarwala noted that there are about 6 billion mobile subscriptions today, growing to 9.1 billion in 2018, and about one billion smartphones, growing to 4.5 billion in 2018. "What this means for networks," he said, "is that the expected growth of network capacity in five years is expected to be 12X over what you have today, and 46% of that will be mobile traffic."
Certainly there has been progress in the past 10 years. Today, Agarwala noted, a two-chip solution can implement an entire multi-standard base station. While a typical IC in 2000 had 40-50 million transistors, today we're planning designs with 3 billion transistors. A number of different types of cores are being pulled into systems, increasing bandwidth requirements. No wonder building a platform such as TI's KeyStone can be a $100 million investment.
Agarwala noted the following "complexities" in mobile infrastructure SoC design:
"Systems knowledge is key" is the primary lesson learned, Agarwala said. "Think back to the $100 million investment required," he said. "You have to figure out where to spend dollars and time in terms of optimization. Don't just optimize at the individual entity level - focus on the system. Are you optimizing the part or are you optimizing the whole?"
Related Blog Posts
Gary Smith at DAC 2013 - the $170M SoC Design is a "Myth"
NI CEO Sounds Call for Platform-based Design at DAC 2013
Cadence CEO at DAC 2013: 'I've Doubled, Tripled Down on Semiconductor Investment'
Freescale CEO at DAC 2013: "Internet of Things" Brings Opportunities, Challenges
Samsung DAC 2013 Keynote: EDA, Semis "Not Well Prepared" for Next Mobile Revolution