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How will NAND Flash memory scale as semiconductor process nodes dip below 20nm? The best combination of cost, power and performance will be found in 3D NAND architectures, according to panelists at a plenary session at the Flash Memory Summit August 13, 2013. But as their lively presentations showed, some questions and challenges remain.
The panel was moderated by Jim Handy of Objective Analysis and was titled "Flash Below 20nm: What is Coming and When?" Panelists were as follows, shown left to right in the photos below:
The panel followed a keynote speech in which two Samsung executives provided some details about their 3D vertical NAND (V-NAND) Flash technology, which according to an August 6 announcement has gone into mass production. The technology offers 128Gb density in a single chip. At the keynote E.S. Jung, executive vice president of Samsung's Semiconductor R&D Center, showed how a V-NAND based SSD offers a 22% faster sequential write, 20% faster random write, 27% lower average power, and 45% lower peak power than a planar NAND-based SSD.
Jim Handy started the plenary session with a problem statement. NAND is shrinking past 20nm, he said, and there are some very large scaling issues - coupling between cells, problems with polysilicon thickness, and problems with the number of electrons per bit. Suppliers are looking at new technologies such as high-K metal, 3D architectures, and alternative memories such as Resistive RAM (ReRAM) and magnetoresistive RAM (MRAM). So where are we going with all this?
The answer was pretty clear -- we're going up to a third dimension. Here are some takeaways from the discussion.
Gill Lee, Applied Materials - Semiconductor Equipment is Ready
Applied Materials has been working on process and equipment technologies for 3D memory for several years now, Lee said, and there's good news - "3D NAND does not require leading-edge lithography. That means manufacturing costs will be much lower than they are for the extension of planar NAND."
However, 3D NAND will require new deposition and etch technologies. 3D NAND will call for high aspect-ratio etch processes, but the number of etches will be far less. "Staircase" etching requires very precise contact landing. Deposition must handle multi-layer stacks and thick films. Equipment is now available to handle these challenges.
"In conclusion, 3D NAND technology will enable continuous scaling of NAND Flash, and the semiconductor equipment industry is ready for this transition at a much lower cost than planar NAND," Lee said.
Chuck Dennison, Micron - Nothing Lower Cost than Vertical NAND
What's up at Micron? Today they're shipping a 16nm NAND, and the company plans to move from there "straight into 3D NAND," Dennison said. "We want to make the transition to vertical NAND, and we're going to do so at the 256Gb level," he said. Dennison noted that Micron's experience with 3D DRAM has helped it overcome some of the challenges of 3D NAND, including the high aspect ratios, atomic layer deposition fill, and large array topology.
With 3D NAND, he noted, manufacturers can pattern 24 or more layers in a single step. Those steps are very challenging, but once the process is in place it's very efficient. "From a cost perspective, we don't see anything lower cost than vertical NAND," Dennison said.
Saied Tehrani, Spansion - Charge Trap Flash Memory
Tehrani spoke about advancements in charge trap flash memory, which can be used for both 2D planar NAND and 3D NAND. Rather than storing charge in conductive polysilicon gates, this technology stores charge in very thin layers of nitrite. One big advantage is that you get two bits per cell. Also, Tehrani said, this technology is easier to manufacture and is much more scalable. Spansion has been working on it for over 10 years.
Tehrani also noted that Spansion has had standalone NOR Flash technology based on the charge trap technology for many years, and that it offers high levels of reliability and performance, Finally, the company has developed charge trap NAND Flash technology. The charge trap cells used in 3D vertical NAND stacks will be very similar to those used today in 2D planar NAND - rather than reading in a 2D plane, you're reading in a 3D axis.
Ritu Shrivastava, SanDisk - Waiting Until the Time is Right
SanDisk is not in a hurry to jump into 3D NAND production. The company's 19nm planar NAND technology is "the lowest cost technology in production," according to Shrivastava. SanDisk 1Y NAND technology will ramp up in the second half of 2013, and 1Z technology will go into volume production in 2015. Finally, the company's BiCS 3D NAND technology will go into production in 2016.
Why the wait? "When we introduce our 3D NAND, we want there to be a meaningful cost reduction over 1Z," Shrivastava said. For some time, he said, 1Z will provide the best scaling at the lowest cost.
Shrivastava said there are still many challenges for 3D NAND, not only in the realm of device physics but in the industry ecosystem as well. The lithography challenge shifts to deposition and etching. High aspect-ratio etching is required for a large number of layers. High volume manufacturing requires new etching equipment and techniques for scaling to a high number of layers.
According to Shrivastava, SanDisk has a three-pronged strategy: 1) scale 2D "as long as we can," 2) then move to BiCS, 3) then move to 3D ReRAM. As for 2D planar NAND, "don't stop at 19nm, don't stop at 1Y, go for a third generation because you have all this investment in the fab and you can get better ROI."
Mark Webb - Consider the Financial Issues
Consultant Mark Webb came with what you might call a reality check. He said that post-20nm scaling will depend on financial issues, not a physics "brick wall."
Webb asserted that planar NAND cost reduction is slowing significantly due to a number of variables. He expects to see little or no cost reduction beyond 15nm. At that point, scaling will effectively step for planar NAND. Actually, he said, planar NAND has two expiration dates - one from 3D NAND, and one from alternative memory technologies.
But 3D NAND is not a walk in the park. It does offer the possibility of returning to historical cost reductions, presuming we use a 40nm half pitch. However, a 16-layer architecture will not reduce cost at any time, a 24-layer architecture will lower costs after four years, and a 32-layer architecture will lower costs after 2.5 years. Webb also offered these predictions:
Myoung Kwan Cho, S.K. Hynix --- Technical Challenges Remain
Cho talked about the 16nm floating gate technology developed by S.K. Hynix, noting that "we have successfully increased bit density per area by around 50% per year." He predicted that floating gate and 3D NAND will "co-exist and compete with each other in terms of reliability, performance and density."
All 3D NAND architectures are facing challenges in yield and retention, Cho noted. Yield improvement calls for stabilization of multi-stack patterning, improved metrology, and defect monitoring deep inside the 3D structure. Despite these challenges, Cho said that S.K. Hynix will have a 3D product by the end of this year.
Flash Memory Summit proceedings are available online for registered conference attendees. Cadence was a sponsor of the conference.
Note: The Flash Memory Summit followed the MemCon conference by one week. Here is some coverage from MemCon 2013:
Scaling the Semiconductor Memory Wall
MemCon Panel: Promises and Pitfalls of 3D-IC Memory Standards
Semiconductor Memory Challenges Will Be Overcome, MemCon Keynoter Says
MemCon Samsung Keynote: New DRAM and Flash Memory Architectures are Needed