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Cadence recently announced its collaboration with TSMC on a custom/analog reference flow for 16nm FinFET-based designs. This collaboration led to a lot of work at Cadence on custom design tools and flows, and some of that work was described in detail at a presentation at the TSMC Open Innovation Platform® Ecosystem Forum (TSMC OIP) on October 1, 2013.
The presentation was titled "Addressing Custom Design Challenges for IP Design at 16nm FinFET Technology" and was given by Jim McMahon, product engineering director at Cadence. McMahon described 16nm FinFET design challenges and showed how a schematic-driven custom IC design flow can meet those challenges. He also talked about new tool features and about key "sub-flows" such as a layout dependent effect (LDE) sub-flow and a parasitic-aware sub-flow.
McMahon noted that Cadence and TSMC have been collaborating on a custom-design 16nm reference flow, and that this work includes collecting technology enablement files from TSMC and pushing them through as complete a design flow as possible. "It's an opportunity for us at Cadence to verify that our tools meet the design challenges of 16nm FinFETs, and it's also an opportunity for us and TSMC to verify that the enablement is correct and complete," he said.
16nm FinFET Design Challenges
For the most part, McMahon said, 16nm design challenges represent an "evolutionary exacerbation" of problems already seen at advanced process nodes. But the 3D nature of FinFET transistors adds some new challenges, such as a 2X increase in the number of parasitics. The FinFET structure also complicates design rule checking (DRC). McMahon identified the following 16nm design challenges:
McMahon showed a 16nm schematic-driven design flow that serves analog/mixed-signal designs. It uses the OpenAccess database to integrate analog and digital flows. Designers on the custom/analog side (Cadence Virtuoso platform) can create analog blocks, import digital blocks, and perform top-level chip assembly in Virtuoso.
In the illustration below, the "custom design realization" graphic on the right includes two layout flows: rapid layout prototyping and detailed layout implementation. The prototyping flow makes it possible for circuit designers to get layout information before the final DRC clean layout is completed.
McMahon said that the rapid prototyping flow lets the circuit designer go through implementation quickly, getting the information he or she needs to do circuit optimization. Designers go through the traditional schematic capture flow and create some design constraints. Designers can then inject some estimated parasitics. There are various ways to do this, including pulling parasitics from previous layouts.
"We provide tools so that you, the circuit designer, can easily realize a placed layout," McMahon said. "You may need assistance from a layout engineer, but the goal is to have the circuit designer drive this as much as possible, pretty much in real time. It takes a few minutes to do a rough placement and then you can bring this back into the simulation environment."
In the detailed layout implementation flow, the goal is to refine and finish placement and routing with minimal impact on electrical performance. "The goal is to create a layout that is correct-by-construction, so the signoff flow is a true signoff flow and not a discovery exercise," McMahon said. The signoff flow includes DRC, layout versus schematic (LVS), electrical rule checking (ERC), extraction, and re-simulation. While this flow is fairly traditional, McMahon noted that Cadence has made "significant enhancements" to handle 16nm design challenges.
LDE: Good Transistors in Bad Neighborhoods
LDEs are not new at 16nm, nor are they specific to FinFETs, but they get worse as process nodes shrink. Thus, any designer at 16nm or below must pay attention to LDEs, because the "neighborhood" or layout context in which a device is placed can significantly impact the performance of the device.
Of particular concern to analog designers, McMahon said, is that LDEs affect device mismatch with differential pairs. He showed an example in which one layout resulted in a mismatch of 1% and another layout resulted in a mismatch of 5%, while the schematic showed no mismatch at all. This is exactly the sort of effect that circuit designers need to know about.
As a result, Cadence and TSMC have collaborated to develop a new, integrated LDE-aware custom design flow. It allows LDE-aware re-simulation using device parameters from partial or completed layout, and pre-layout LDE analysis. The flow provides a direct link between the TSMC LDE-API and the Cadence Litho Electrical Analyzer (LEA). The flow has been validated for TSMC 28nm, 20nm, and 16nm processes. (A recent webinar described this flow in detail—see this blog post for a review).
McMahon noted that TSMC and Cadence have also done a great deal of work on a parasitic-aware design flow. This flow provides solutions including the TSMC Macro Device Plug-In, Cadence VPAD parasitic estimation, and TSMC Pseudo Parasitic Device Library.
Commenting on a case study, McMahon noted that a regular design style works best for FinFETs. This calls for a row-based layout style, a standardized row height, and a limited set of FinFET lengths. The end result is a "tile structure" that allows designs to be put together very quickly. There may be some tradeoff in area and performance, but there's also a time-to-market advantage.
In summary, McMahon said, Cadence and TSMC have developed a complete design flow that addresses 16nm FinFET design challenges. A reference design database, presentations for key sub-flows, and associated tutorials are available for download from the TSMC-Online website.
Related Blog Posts
TSMC OIP Forum: 16nm FinFETs, 3D-ICs Gain EDA and IP Support
TSMC OIP: On the Road to the Silicon Super Chip