Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Engineers at a leading IC design services company recently came up with a novel approach that improves verification efficiency by "layering" sequences of transactions to reach higher levels of abstraction. The approach is based on the Universal Verification Methodology (UVM), which defines a reusable UVM Verification Component (UVC) that, among other tasks, provides stimulus to the design under test using sequences.
This methodology was presented at the recent CDNLive India 2013 conference by Gaurav Jalan (right), Director of Engineering at SmartPlay Technologies, a global leader in VLSI design services. The paper, titled "UVM Sequence Layering in Configurable Memory Controller Verification," won a best paper award. Presentation slides are available online, as described at the end of this post. Jalan also writes a functional verification blog.
In an interview, Jalan described the problem they were trying to solve and the reasons for introducing a new methodology. He noted that his team was asked to verify a highly configurable DRAM memory controller with over 400 possible configurations. They were provided with raw RTL and a specification by the customer, and their task was to define a verification strategy using SystemVerilog and UVM, come up with an executable verification plan, develop a verification environment using Cadence verification IP (VIP), and "execute verification from scratch to closure."
Traditional and New Approach
The design under test (DUT) supported multiple protocols on both the processor interface and the DRAM interface. In a conventional verification approach, engineers would develop test sequences targeting each protocol on the processor side, and develop scoreboards for each protocol on the DRAM side. In this approach each configuration works as a separate DUT, and additional time is required to develop all the sequences for different configurations. The conventional approach also poses limitations when it comes to reusability, portability, scalability, and maintainability.
In the conventional approach, Jalan said, "the overall reusability index was low. To avoid this, we decided to move a level up - define tests and sequences based on the test plan at a higher, protocol-agnostic level that would be translated at run time into the desired protocols based on configuration. This concept is called sequence layering."
With sequence layering, engineers can develop test scenarios that are protocol independent. As shown below, the layering is achieved by a "layering agent" derived from uvm_agent. The layering agent has a monitor and a sequencer, and it "bundles" (translates) protocol-level transaction items into higher-level sequence items. A lower level sequencer translates the abstract level sequences into protocol-specific sequences, and pushes them forward to a driver.
"The way it [layering agent] works," Jalan said, "is that there is a high-level sequence item associated with the layering sequencer. It would connect to the sequence of the lower level protocols using the same mechanism as is used by the sequencer and driver in an uvm_agent. The lower level sequence would have only one sequence running as a ‘forever' thread. Inside this sequence we have a get_next_item similar to what we do in a uvm_driver. The item is received from the higher level sequencer. It is translated by the lower level sequencer and given to its driver. The response is then passed back to the layered sequencer, indicating that the lower level sequencer is ready for the next item."
The layering approach allows engineers to create generic sequences that are reusable across protocol interfaces. An example of a higher-level scenario might be, "Burst Read followed by a Burst Write in the same row." Protocol-specific coverage ensures that all scenarios are covered.
Faster Turnaround Time
The net result was a quicker turnaround time for each DUT configuration. Jalan said that the extra effort required to build the layering agent was 6%, but engineers saved almost 25% overall time later when developing sequences and tests. The overall project effort was 100 man-months. The effort included the use of Cadence ePlanner to develop an executable verification plan, Cadence eManager to track regressions and coverage, Cadence VIP for processor interfaces, and Denali models (from Cadence) for memory interfaces. The Cadence VIP team provided "excellent" support, Jalan said.
To view the CDNLive! India paper, click here. You will be asked for your Cadence log-in (or to sign up for one - a quick and easy process). You will then see a menu of proceedings from seven tracks. Choose track 5, "Functional Verification Track II," and scroll down to the paper titled "UVM Sequence Layering in Configurable Memory Controller" by Ghouse Syed Sherraj and Gaurav Jalan.