Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
It's easy to be confused by the alphabet soup of acronyms that surrounds static timing analysis (STA). At the Signoff Summit at Cadence headquarters on Nov. 21, 2013, Igor Keller, senior R&D architect at the company, explained several on-chip variation (OCV) approaches that provide some of the advantages of statistical STA (SSTA) without its relatively high costs.
Ten years ago, as I well remember, SSTA was poised to become one of the next big things in IC design. It made sense. Rather than returning a single timing number, SSTA could return a statistical distribution. It could tell you, for example, that you have an 80% chance of hitting a given timing number. But the development of SSTA libraries proved to be a stumbling block.
"Statistical timing is a great approach," Keller said. "It's the most accurate I can think of, but it's also the most expensive. Except for IDMs, nobody could really deploy it in production because it required too much run time and memory."
Alternatives to SSTA
Keller reviewed several approaches for handling in-die variations at advanced nodes, starting with plain old OCV analysis. OCV provides a single derating factor for all instances. Results can be grossly optimistic or pessimistic. As Keller noted, you may not be able to close your timing without leaving a lot of performance on the table.
Keller noted that the distinction between local and global variations is very important with OCV. You can handle global variations with corners (best case, nominal, and worst-case combinations) but corner analysis is very difficult with local variations. These variations "do not correlate statistically, and they have a profound effect on OCV," he said. "The biggest challenge in OCV variations today is handling the local uncorrelated variables."
Advanced OCV (AOCV), sometimes referred to as location-based OCV (LOCV), is aimed at reducing pessimism. It provides variable derating for min/max, cell, arc, and stage count. Libraries can be created from existing SSTA characterization tools. The graphic below shows the OCV and AOCV derates compared to an "ideal" derate.
AOCV, however, assumes similar statistical variability between cells regardless of slew and load. It can still be very optimistic or pessimistic compared to SSTA. "You cannot assume that all your instances on the path are the same cells," Keller said. "You cannot assume that all the input slews are the same. People realized that you cannot really reduce pessimism a lot with AOCV." In particular, he said, stage count is a "flaky number" that can generate a lot of pessimism.
Keller had relatively little to say about parametric OCV (POCV), other than its elimination of stage count as a parameter. It represents one more step towards SSTA but still does not resolve the delay dependency on slew and load.
Statistical OCV in the Sweet Spot?
Statistical OCV (SOCV) is a simplified approach to SSTA that uses a single local variable. It solves the major limitations of AOCV, including variation dependency on slew and load, and the assumption that the same cell, or load, is in the path. It promises near SSTA accuracy for a small additional cost of runtime and memory compared to AOCV, and it can include signoff-accurate signal integrity (SI) analysis.
"You handle global variations by going to corners," Keller said. "The corner based approach is well understood by engineers. At the same time, you push the tricky part of the variation - which is local variation - into statistical. You compress everything into one variable and that's your statistical OCV."
Keller said that SOCV is a "version of SSTA which is not as expensive as statistical timing, yet is almost as accurate." SOCV also has a "look and feel" that is familiar to users of STA. Users who want to see a single flat timing number report, as they would for STA, can continue to do so. SOCV can also provide a three-sigma statistical distribution for those who want to see it.
According to Keller, SOCV is much more accurate than AOCV, especially for graph-based analysis AOCV. The SOCV timing flow is very similar to the "regular" timing flow. SOCV can be validated with SPICE Monte Carlo analysis.
In conclusion, Keller said, "SOCV brings you advantages over other approaches by doing a more accurate analysis in terms of dependency on slew and load." It's a proven technology, he said, and automated flows exist for library generation.
So, maybe full SSTA wasn't the "next big thing" in IC design after all - but it has clearly inspired some new and more accurate approaches to timing analysis.
Note: This was one of a number of presentations in the day-long Cadence Signoff Summit, which also included updates on the Cadence Voltus IC Power Integrity Solution, Tempus Timing Signoff Solution, signoff extraction, incremental metal fill, path-based timing analysis, physical verification signoff, and design for manufacturability. Presenters included Cadence R&D experts and customers. Presentations will be archived online at a later time.