Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
You don't hear much about RTL synthesis or design for test (DFT) these days, probably because many people think these are long-solved problems. But according to speakers at the Cadence Front-End Design Summit Dec. 5, 2013, both RTL synthesis and DFT are rapidly evolving to keep up with the demands of advanced IC process nodes and "Giga-gate" chips.
Ankush Sood (right), R&D director at Cadence, gave a presentation titled "Addressing Physical Challenges Early in RTL Synthesis." He talked about the need for "physically aware" synthesis, the technologies and optimizations it requires, and synthesis capabilities needed for advanced nodes, such as layer-assignment optimization.
Mike Vachon, engineering group director for Encounter Test at Cadence, offered a presentation titled "Scalable Test Methodology for Large SoC Designs." After a brief review of Cadence Encounter Test products, he discussed test approaches for Giga-gate designs including distributed processing for automatic test pattern generation (ATPG), test point insertion, and hierarchical test using IEEE 1500 based wrappers.
The one-day FED Summit also included speakers from Cisco, Qualcomm, Texas Instruments, and Omnivision, in addition to Cadence R&D. Presentations will be available at a later time.
Let's get physical
Sood's talk was aimed at showing why physically aware synthesis is needed, and why it has to occur earlier in the design flow than it has so far. "We have been talking about physical synthesis for 20 years, but a lot of it has been about physical optimization, not really physical synthesis," he said. "We want to make the entire flow physically aware from the first time you try to optimize anything to the point of handoff."
So why the need for early physically aware synthesis? One reason is that wires dominate delays at 45nm and below, and wire-load models become increasingly inaccurate. Another important reason comes down to cost. "Every extra dollar in the front end can save ten dollars later on," Sood said. "You can spend a lot less time trying to optimize later."
The Cadence RTL Compiler 13.1 supports GHz performance with power savings, congestion optimization, and tight correlation to the Encounter Digital Implementation System. The release includes physically aware structuring, physically aware mapping, and physically aware DFT. The release also supports a hierarchical flow using interface logic models (ILMs).
One key technology is cluster placement. Sood showed a comparison of early cluster-based placement to the detailed placement in Encounter, and the correlation appeared to be very close. Cluster-based placement, of course, runs much faster.
Sood discussed case studies in which:
In his discussion of advanced nodes, Sood noted that different metal stacks have different resistance and capacitance characteristics. Designers need to predict where the interconnect will go. In one comparison he showed, M1 resistance/length (ohms/micron) was 20.56 while M9 resistance/length was 0.05. Conclusion: Buffering and gate optimization is not enough—you need to optimize wire topology and layer assignment as well.
Other requirements that Sood cited for advanced node synthesis include leakage optimization, improved slew degradation estimation, and advanced on-chip variation (AOCV) support.
DFT for Giga-gate designs
Mike Vachon (left) focused on test generation for very large designs. He noted that Cadence is now seeing designs as large as 300 million instances, and designs of that size drive some new requirements. DFT is not only about coverage and data volume, but also tool capacity and run time—"challenges we haven't faced in the past when designs were much smaller."
Many design teams run ATPG flat—but for large designs, run times are becoming increasingly unmanageable, stretching into days or weeks. One approach is to wrap and isolate cores using the IEEE-1500 Embedded Core Test standard. In this way, engineers can generate patterns for one core at a time, and do some interconnect testing at the top level.
However, ATPG turnaround times will still be a challenge. Cadence offers a distributed (parallel processing) capability for ATPG that can make a big difference. Vachon showed how four CPUs can achieve a 3.7X speedup compared to one CPU, and how 16 CPUs can achieve a 14.3X speedup. A 32-way CPU mode, combined with pattern compaction, was able to achieve a nearly 50% pattern reduction.
Test point insertion can reduce pattern count and improve coverage—but it also adds area. A capability called Random Resistant Fault Analysis (RRFA), targeted at logic built-in self test (LBIST), looks at portions of a design that would be difficult to test with random patterns. It then suggests locations for inserting test points.
Finally, Vachon talked about the importance of hierarchical test generation. If you have two identical cores, you can generate the same test patterns once and apply them to both instances. To achieve this result, Cadence uses IEEE 1500 core-based testing with hierarchical test compression. Vachon showed how the hierarchical flow works within the RTL Compiler cockpit and the Encounter Test ATPG product.
Hierarchy is a choice. "For those who want to run very large designs flat, we're ensuring that our run-time capacity is continuing to scale," Vachon concluded. "But we are also investing heavily in hierarchical test to allow customers to decompose test problems with very large designs, and to scale back the complexity and run times."