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When you're in a rapidly expanding marketplace that is coming into mainstream adoption, you want to have the most complete solution possible. And that is some of the thinking behind the Cadence acquisition of high-level synthesis (HLS) pioneer Forte Design Systems, which was announced Feb. 5 and is now completed.
Unlike RTL synthesis or "logic synthesis," HLS works at a much higher level of abstraction. Both the Cadence C-to-Silicon Compiler and the Forte Cynthesizer products take in IEEE 1666 SystemC code and constraints and output RTL code. Compared to conventional RTL design, the HLS methodology offers much faster time to market, faster and easier verification (fewer lines of code means fewer bugs), and an ability to quickly generate different micro-architectures and compare power, performance, and area.
A decade ago, HLS was pretty much limited to a handful of large Japanese consumer product companies. But now, said Michał Siwiński, vice president of product marketing at Cadence, it has spread across the globe and it enjoys strong adoption in many systems and semiconductor companies for a wide variety of applications. The chart below shows some of the end applications served by C-to-Silicon Compiler, which can handle datapath, control, and mixed datapath and control logic.
While both C-to-Silicon Compiler and Cynthesizer are SystemC-based HLS tools, each has its strengths. With an RTL synthesis engine under its hood, C-to-Silicon Compiler can give good quality of results for both control and datapath. It also offers incremental ECO support. Cynthesizer offers strong advanced datapath synthesis, and can perform memory scheduling for parallel and pipelined architectures. It also provides an IP library with floating-point datatypes, which is an important feature for some of the application segments.
Cynthesizer dates back to 2001, the same year that CynApps and Chronology merged to form Forte. Last year Forte announced Cynthesizer 5, a major upgrade that helps users create reusable SystemC models and improve design and verification time. By combining scheduling with resource allocation, the new release improves predictability and quality of results.
Additionally, Forte brings with it Cynthesizer Low Power, which makes complex power optimizations that are often difficult or impossible to realize with hand-coded RTL. Moreover, Cynthesizer 5 comes with a new Workbench SystemC IDE (integrated development environment) that eases SystemC development.
The CynWare SystemC IP Library and the CynWare Interface Generator give Cynthesizer 5 users synthesizable building blocks to jump-start their designs. The library contains high-speed simulation models and bit-accurate synthesizable models for all IP, including floating point datatypes, user-configurable connectivity interfaces, clock domain crossing circuitry, and specialized communications interfaces. Finally, Forte's DpOpt technology can automatically identify optimization opportunities in SystemC code.
Following its acquisition of Arithmatica in 2009, Forte also offered CellMath, a library of differentiated datapath IP for high-value functions. With CellMath, IC designers can implement major blocks of datapath functionality in a fraction of the time it would take to develop it internally from scratch.
Cadence C-to-Silicon Compiler, introduced in 2008, also has some unique features. For example, by encapsulating the Cadence Encounter RTL Compiler under the hood, it can provide signoff-quality RTL for both datapath and control-oriented designs. Thanks to RTL Compiler, C-to-Silicon Compiler can also synthesize all the way from SystemC transaction-level models (TLM) down to gates.
Handling Control and Datapath
C-to-Silicon Compiler is known for balanced handling of control and datapath designs, a graphical analysis capability for micro-architectural exploration, and tight integration into the Cadence Encounter digital design flow. Along with the Cadence Incisive functional verification platform, C-to-Silicon Compiler has enabled a TLM design and verification methodology that helps customers shorten the associated verification cycles and prove design quality. (This TLM methodology is described in a 2010 book).
C-to-Silicon Compiler also has an incremental ECO capability that makes it possible to generate a "patched" RTL design that will meet timing constraints downstream. Working in conjunction with the Cadence Conformal ECO Designer, this capability enables the patch to be applied to the netlist, the placed design, the routed design, or the post-mask netlist.
The Cadence and Forte HLS customer databases are largely complementary. Key customers are different for each company. Forte is slightly stronger with the mobile systems companies, and will provide Cadence with broader access to mobile companies, while Cadence is a bit stronger on the consumer side and with key semiconductor companies.
Putting It All Together
Before the acquisition, Siwiński observed, "There were good offerings, but really no complete [HLS] offerings that provided what customers have increasingly been asking for. Now we can put together a more comprehensive solution that will further accelerate adoption of this exciting technology."
This more complete offering, Siwiński said, will overcome some of the obstacles to HLS adoption. No more will customers hesitate to adopt HLS because it doesn't have floating-point IP, or because it doesn't have signoff-quality results for both control and datapath logic. "We now have an expanded R&D team of brilliant innovators, a larger set of best-practices collateral and training material, and a broader field organization to more effectively support customer deployments of this technology," he added.
For now, given the largely complementary technology behind the offerings, Cadence will continue to sell both C-to-Silicon Compiler and Cynthesizer. "We are fully committed to supporting our customers. No product is being discontinued now," Siwiński said.
Ultimately, the Forte acquisition will help Cadence further drive a SystemC standard flow for design and multi-language verification. As such, it fits into a broader system-level design strategy that also includes the System Development Suite, a set of connected hardware/software development platforms.
"It's about changing the way we do design and verification, starting with the end product as the key goal, and providing the best system design enablement," Siwiński added. "We are now helping customers make this real. Our focus is going to be on helping customers adapt system-level technology such as HLS as the shift from RTL to TLM continues, just as there was a shift from gates to RTL in the early 90s. It's about time."
Related Blog Posts
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Forte and Cadence at DAC: How to Deploy High-Level Synthesis
New Capabilities in the C-to-Silicon Compiler 2013 Releases