Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Much has been written (some by me) about the challenges of timing closure for IC designers. It turns out that timing closure is increasingly a problem for PCB designers as well. The Cadence Allegro TimingVision environment, announced today (March 5, 2014), is an innovative solution that combines an embedded timing engine, color-coded real-time visual feedback (shown at right), and auto-interactive technologies for delay and phase tuning.
PCB designers, like IC designers, are under increasing pressure to rapidly turn out products that are faster, have more bandwidth, and use less power. This pressure is leading to the increased use of high-speed standard interfaces, like DDR3 or DDR4. Timing relationships for these interfaces are complex, with complicated matching requirements. Tuning signals for these interfaces is a frustrating and time-consuming project.
Meanwhile, supply voltages have decreased from 1.8V to 1.5V and 1.2V. In consequence, signals are very sensitive to ripples in the power supply. A ripple that was tolerable at 1.8V may not be tolerable at 1.2V. Finally, signals are closer together because form factors are smaller, increasing the odds of crosstalk.
Constraints are getting more complex because of sensitivity, and because higher speed signals require tighter tolerances and tighter margins. "That translates into a complex set of electrical and layout implementation constraints," observed Hemant Shah, product marketing group director at Cadence.
Thrashing Back and Forth
Interdependencies between signals are a major challenge, according to Shah. "A change in one signal in one group will cause a problem in other groups," he said. "PCB designers have to plan tuning as well as routing, and pick the right set of signals to tune first. Otherwise they will be thrashing back and forth. They'll fix one signal, find a problem with another one, fix the other one and then have a problem in the first one. This is a trial and error process with current technology."
PCB designers can get some help from the Allegro Constraint Manager, which shows whether signals are in compliance with constraints (green for yes, red for no). However, designers have to go back and forth between the design canvas and Constraint Manager, which does not provide physical information. Feedback is provided on a matched group level, and all signals have to meet timing for the group to go "green." Interdependencies and margins between groups are calculated by the designer manually.
Providing a new level of support for PCB timing closure, the Allegro TimingVision environment includes these three components:
The illustration below shows how AiPT can help designers to meet differential pair phase requirements. AiPT offers both static and dynamic phase compensation. Once nets are selected, a variety of user-driven compensation techniques can be deployed.
TimingVision offers a DRC Timing Mode, Smart Timing Mode, and Smart Phase Mode. DRC Timing Mode ensures compliance as a design nears completion. Smart Timing Mode identifies critical signals and defines timing closure goals for the user with real-time feedback. Smart Phase Mode identifies exact sections of differential signals that require tuning to meet phase skew goals.
In the illustration at the top right, red indicates the target mode, and the bottom-most yellow signal is the longest signal. Working in DRC mode, the designer will try to match the other signals to the longest signal. Signals will not go green until they are within tolerance of all other signals in the match group.
In the Smart Timing Mode depicted at the lower right, the embedded timing engine identifies a new target signal (formerly the bottom-most yellow signal). The timing engine calculates new min/max "goals" based on the signals in the interface. Signals go green as each one meets the independent min/max goal.
While not a requirement, TimingVision can be coupled with Sigrity power-aware signal integrity analysis software. "This really ensures that your interfaces are in spec," Shah said. TimingVision plus Sigrity lets users model simultaneous switching noise, perform signal and power integrity simulations, predict bit error rate, enable power integrity signoff, and run package and model extraction for system-level analysis. Shah noted that the TimingVision environment can be used for IC package design as well as PCB design.
In a success story at Cadence.com, Taiwanese computer manufacturer Pegatron used the AiDT feature in Allegro PCB Designer. The company reported up to a 67% faster routing process and a 75% reduction in engineering resources required for routing and tuning.
TimingVision is available now as part of the Allegro PCB Designer High-Speed Option. A landing page with further information is available at Cadence.com.