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While several key drivers are propelling semiconductor industry growth, the technical challenges are acute and the end markets are demanding. And that opens new opportunities for Cadence and its ecosystem partners, according to Lip-Bu Tan, president and CEO of Cadence.
Tan spoke at the CDNLive Silicon Valley user conference March 11, 2014, in a keynote speech titled "An Executive View of Trends and Technologies in Electronics." He outlined three key growth drivers for semiconductors, discussed end markets and technology challenges, noted several key Cadence technology announcements over the past year, and explained the importance of a robust ecosystem of foundry and semiconductor IP partners.
The three growth drivers are mobility, cloud computing, and the Internet of Things. Consumers today expect to have access to information anywhere, Tan noted. A few numbers quickly illustrate the demand for mobility. Tan said that over one billion smartphones were shipped last year and that analysts are projecting that 250 million tablets will ship in 2014.
With a compound annual growth rate (CAGR) of 55%, cloud computing is turning into a huge market, Tan said. "Your pictures, your videos, will be in the cloud and you won't have to worry about storage limitations." He also pointed to software as a service (SaaS) as a cloud opportunity. Finally, the Internet of Things is expected to produce 50 billion devices by 2020.
End Market Challenges
To gain more familiarity with end markets, Tan spent two days "just walking around" at this year's Consumer Electronics Show. He saw wearable electronics, curved TVs, automotive entertainment, and "all kinds of connected, cloud-enabled devices." While these breakthroughs are fascinating, they pose a number of system design requirements, including low power, mixed-signal, advanced node, "relevant" IP, and system verification.
Tan pointed to a new breed of vertically aggregated companies. He noted that a new breed of systems companies has decided to optimize all the way from the system-on-chip (SoC) level to the board, package, and system. "This is a very exciting change for our industry," he said.
IP and SoCs Get More Complex
Moving on to technology challenges, Tan noted the growing complexity of standard interfaces. DDR3, for example, is about 3X the complexity of DDR1, and PCI Express Gen2 is about 2X the complexity of PCI Express Gen1.
At the SoC level, he noted, more IP cores must be integrated and verified. According to one report, there were only six cores per SoC at the 180nm process node, but there will be an average of 123 cores per SoC at the 14nm node.
To help design teams cope with the complexity, Cadence has been "quietly building up our IP portfolio," Tan said. He noted that an 800-member R&D team is focused on providing "silicon-proven, high-quality IP." Cadence design IP is focused on such applications as memory, high-speed connectivity, audio, and video. And Cadence has a very broad verification IP (VIP) portfolio as well, Tan reminded listeners.
Cadence offers an extensive IP portfolio for SoC design
Last year Cadence acquired Tensilica, a provider of dataplane processing units (DPUs). Tan reviewed some recent highlights with Tensilica audio and video processor IP, including video processing and stabilization, face detection and tracking, gesture recognition, always-on listening for voice control, and sensor fusion and context awareness.
A Busy Year for New Technology
Tan reviewed some key EDA technology and product announcements at Cadence during the past year, including:
He also noted that Cadence is "investing heavily" in 2.5D and 3D IC packaging technology. And Cadence is bringing signal-integrity analysis into its Allegro PCB product line following the 2012 purchase of Sigrity.
Looking toward the future, Tan showed a chart that notes that 80% of SoC development costs at 16nm will come from software, verification, and validation. The solution, he said, is to move from the register-transfer level (RTL) of abstraction to transaction-level modeling (TLM). The recent Cadence purchase of Forte Design Automation is part of this move. The combination of Cadence and Forte, Tan said, will result in a "very compelling" high-level synthesis offering.
Tan also discussed the new "hybrid" verification methodology for embedded software development, which combines the advantages of virtual platform models with emulation. Basically, the RTL design runs in the Palladium XP emulation platform (left) while high-speed, highly abstract processor models run on a workstation. The advantages, he said, are that software validation can start up to six months earlier, and users can boot an OS 60X faster than they could with emulation alone.
"I think you can see," Tan said, "that we are moving up from IC and SoC design. We are moving to system design enablement and we provide PCB design, signal integrity analysis, hardware/software verification, system analysis, and also system-level IP. All in all, we continue to build on what we have to help you with your designs."
Cadence can't do this alone, Tan concluded—a robust IP and foundry partner ecosystem is essential for success. "Our goal is to be the trusted partner," he said. "Together we can drive success into the marketplace."
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